Inventor

SCHOINAS IOANNIS T

US50 patents

⚠️ This page may combine multiple inventors who share the name “SCHOINAS IOANNIS T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHOINAS IOANNIS T

INTEL CORP

Flexible event monitoring counters in multi-node processor systems and process of operating the same

Launching a secure kernel in a multiprocessor system

Storing directory information for non uniform memory architecture systems using processor cache

System, apparatus and method for page granular, software controlled multiple key memory encryption

Launching a secure kernel in a multiprocessor system

Method, apparatus, system for qualifying CPU transactions with security attributes

Method, system, and apparatus for dynamic reconfiguration of resources

Launching a secure kernel in a multiprocessor system

Launching a secure kernel in a multiprocessor system

Launching a secure kernel in a multiprocessor system

Cryptographic memory ownership

Composable trustworthy execution environments

Cryptographic system memory management

Partitioning access to system resources

Arbitrating memory accesses via a shared memory fabric

Providing multiple roots in a semiconductor device

Secure stream protocol for serial interconnect

Cryptographic system memory management

Secure stream protocol for serial interconnect

Providing isolation in virtualized systems using trust domains

Cryptographic system memory management

Launching a secure kernel in a multiprocessor system

Composable trusted execution environments

Data release control based on authentication and link protection

System, apparatus and method for page granular, software controlled multiple key memory encryption

Securing platform link with encryption

Data release control based on authentication and link protection

System, apparatus and method for page granular,software controlled multiple key memory encryption

Securing platform link with encryption

Multi-key cryptographic memory protection

Launching a secure kernel in a multiprocessor system

Reconfiguring a secure system

Launching a secure kernel in a multiprocessor system

Dynamic interconnect width reduction to improve interconnect availability

Method, apparatus, system for representing, specifying and using deadlines

Method for enforcing resource access control in computer systems

Launching a secure kernel in a multiprocessor system

System, apparatus and method for tunneling validated security information

WILSON JOHN H

Launching a secure kernel in a multiprocessor system

Launching a secure kernel in a multiprocessor system

Launching a secure kernel in a multiprocessor system

AYYAR MANI

Method, system, and apparatus for dynamic reconfiguration of resources

Method, system, and apparatus for dynamic reconfiguration of resources

Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components

SASTRY MANOJ R

Method for enforcing resource access control in computer systems

Incorporating access control functionality into a system on a chip (SoC)

CHERUKURI NAVEEN

Replacing cache lines in a cache memory based at least in part on cache coherency state information

DATTA SHAM M

Reconfiguring a secure system

GROBMAN STEVEN L

Securing inputs from malware

SCHOINAS IOANNIS T

Separable transport layer in cache coherent multiple component microelectronic systems