Inventor
JOYNER JODY B
US41 patents
⚠️ This page may combine multiple inventors who share the name “JOYNER JODY B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
35 patentsUS6553442B1Apr 22, 2003
Bus master for SMP execution of global operations utilizing a single token with implied release
IBM36 citations93
US6516368B1Feb 4, 2003
Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release
IBM27 citations93
US6507880B1Jan 14, 2003
Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens
IBM25 citations93
US6502171B1Dec 31, 2002
Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data
IBM48 citations93
US6477613B1Nov 5, 2002
Cache index based system address bus
IBM25 citations93
US6460101B1Oct 1, 2002
Token manager for execution of global operations utilizing multiple tokens
IBM20 citations93
US6353875B1Mar 5, 2002
Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions
IBM47 citations93
US6343344B1Jan 29, 2002
System bus directory snooping mechanism for read/castout (RCO) address transaction
IBM43 citations93
US6343347B1Jan 29, 2002
Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction
IBM49 citations93
US6275909B1Aug 14, 2001
Multiprocessor system bus with system controller explicitly updating snooper cache state information
IBM48 citations93
US10318435B2Jun 11, 2019
Ensuring forward progress for nested translations in a memory management unit
IBM6 citations84
US7779148B2Aug 17, 2010
Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips
IBM15 citations84
US6480915B1Nov 12, 2002
Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release
IBM16 citations84
US6442629B1Aug 27, 2002
Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release
IBM15 citations84
US6349367B1Feb 19, 2002
Method and system for communication in which a castout operation is cancelled in response to snoop responses
IBM18 citations84
US6338124B1Jan 8, 2002
Multiprocessor system bus with system controller explicitly updating snooper LRU information
IBM18 citations84
US6279086B1Aug 21, 2001
Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position
IBM16 citations84
US6460100B1Oct 1, 2002
Bus snooper for SMP execution of global operations utilizing a single token with implied release
IBM11 citations74
US6324617B1Nov 27, 2001
Method and system for communicating tags of data access target and castout victim in a single data transfer
IBM6 citations74
US6321305B1Nov 20, 2001
Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data
IBM13 citations74
US9378144B2Jun 28, 2016
Modification of prefetch depth based on high latency event
IBM3 citations73
US9218292B2Dec 22, 2015
Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler
IBM4 citations73
US9213647B2Dec 15, 2015
Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning scheduler
IBM2 citations63
US7827428B2Nov 2, 2010
System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
IBM4 citations63
US6601145B2Jul 29, 2003
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls
IBM5 citations63
US6546468B2Apr 8, 2003
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update
IBM2 citations63
US6546469B2Apr 8, 2003
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers
IBM6 citations63
US10884943B2Jan 5, 2021
Speculative checkin of ERAT cache entries
IBM0 citations62
US10599569B2Mar 24, 2020
Maintaining consistency between address translations in a data processing system
IBM1 citations62
US9384136B2Jul 5, 2016
Modification of prefetch depth based on high latency event
IBM2 citations62
US10671537B2Jun 2, 2020
Reducing translation latency within a memory management unit using external caching structures
IBM0 citations52
US10649902B2May 12, 2020
Reducing translation latency within a memory management unit using external caching structures
IBM0 citations52
US10380031B2Aug 13, 2019
Ensuring forward progress for nested translations in a memory management unit
IBM0 citations52
US7921316B2Apr 5, 2011
Cluster-wide system clock in a multi-tiered full-graph interconnect architecture
IBM0 citations52
US6546470B1Apr 8, 2003
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation
IBM0 citations52