Inventor

FLETCHER THOMAS D

US66 patents

⚠️ This page may combine multiple inventors who share the name “FLETCHER THOMAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FLETCHER THOMAS D

INTEL CORP

Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit

Processor having execution core sections operating at different clock rates

Clocking scheme for latching of a domino output

Method and apparatus for clock skew compensation

Systems, apparatuses, and methods for chained fused multiply add

Pulsed clock signal transfer circuits with dynamic latching

Processor having execution core sections operating at different clock rates

Apparatus, method and system for a ratioed NOR logic arrangement

Multi-level, low voltage swing sensing scheme for high speed memory design

Method and apparatus for pulsed clock tri-state control

Apparatus, method and system for pulse passgate topologies

Apparatus, method and system for providing LVS enables together with LVS data

Method and apparatus for global bitline multiplexing for a high-speed memory

Temperature measurement and compensation scheme

Processor having execution core sections operating at different clock rates

Method and apparatus for correcting a clock duty cycle in a clock distribution network

Global clock self-timed circuit with self-terminating precharge for high frequency applications

High speed ratioed CMOS logic structures for a pulsed input environment

Compressing music into a digital format

Systems, methods, and apparatuses for heterogeneous computing

Vector mask driven clock gating for power efficiency of a processor

Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path

Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices

Systems, apparatuses, and methods for chained fused multiply add

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Processor having execution core sections operating at different clock rates

Vectored flip-flops and latches with embedded output-merge logic and shared clock drivers

Shape-based image compression/decompression using pattern matching

Generating a 2-phase clock using a non-50% divider circuit

Instruction and logic for multiplier selectors for merging math functions

Systems, methods, and apparatuses for heterogeneous computing

Systems, apparatuses, and methods for chained fused multiply add

High gain pulse generator circuit with clock gating

Variable width pulse generator

Functional unit capable of executing approximations of functions

Symmetric cascaded domino carry generate circuit

Cascaded domino four-to-two reducer circuit and method

NORTH AMERICAN PHILIPS CORP SI

CMOS driver circuit having reduced switching noise

Switching device with dynamic hysteresis

Edge-sensitive dynamic switch

Voltage translator with restricted output voltage swing

PHILIPS CORP

Differential input buffer-inverters and gates

Circuit suitable for differential multiplexers and logic gates utilizing bipolar and field-effect transistors

SIGNETICS CORP

Bipolar logic gate including circuitry to prevent turn-off and deep saturation of pull-down transistor

Voltage signal translator

CORBAL JESUS

Instruction and logic to provide vector linear interpolation functionality

Super multiply add (super madd) instruction

PINEIRO JOSE-ALEJANDRO

Math circuit for estimating a transcendental function

SAGER DAVID J

Processor having execution core sections operating at different clock rates