Inventor

OGIUE KATSUMI

JP36 patents

⚠️ This page may combine multiple inventors who share the name “OGIUE KATSUMI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OGIUE KATSUMI

HITACHI LTD

Semiconductor IC device having a RAM interposed between different logic sections and by-pass signal lines extending over the RAM for mutually connecting the logic sections

Semiconductor integrated circuit

Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit

Semiconductor integrated circuit with dummy pedestals

Method of manufacturing semiconductor integrated circuit device

Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array

Semiconductor integrated circuit device

MOS/bipolar device with stepped buried layer under active regions

Isolation regions formed by locos followed with groove etch and refill

Semiconductor memory system for use in logic LSI&#39;s

Method of manufacturing a semiconductor integrated circuit device

Semiconductor body, and device formed therefrom, having grooves with silicon nitride on the groove surfaces

Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove

Method of manufacturing semiconductor device with constant width deep groove isolation

Semiconductor integrated circuit device having bipolar memory, and method of manufacturing the same

Semiconductor integrated circuit

Semiconductor integrated circuit

Semiconductor integrated circuit

Method for fabricating a semiconductor integrated circuit device having thick oxide films and groove etch and refill

Semiconductor integrated circuit device with two variable delay lines in writing circuit control

Semiconductor integrated circuit with bipolar transistors and mosfets

Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and i/o unit circuit of the gate array

Semiconductor integrated circuit device

Semiconductor memory device

Method of forming trench isolation in an integrated circuit

Semiconductor integrated circuit device and method of producing same

Semiconductor memory system for use in logic lsi&#39;s

Semiconductor integrated circuit

Semiconductor integrated circuit device with isolation grooves and protruding portions

High speed bipolar-MOS logic circuit including a series coupled arrangement of a bipolar transistor and a logic block having a MOSFET

Method of manufacturing a semiconductor device

Method of making semiconductor integrated circuit device

Semiconductor memory device providing a selection circuit change-over arrangement

Semiconductor integrated circuit

VLSI TECHNOLOGY RES ASS

Packaged semiconductor device structure including getter material for decreasing gas from a protective organic covering

HITACHI IND

Method of fabricating a semiconductor substrate, and semiconductor device, having thick oxide films and groove isolation

Semiconductor memory system for use in logic LSI's

Semiconductor memory system for use in logic lsi's