Inventor

ARBEL YGAL

US52 patents

⚠️ This page may combine multiple inventors who share the name “ARBEL YGAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARBEL YGAL

XILINX INC

Circuits for and methods of preventing unauthorized access in an integrated circuit

High bandwidth chip-to-chip interface using HBM physical interface

Clock monitor

Configurable network-on-chip for a programmable device

End-to-end quality-of-service in a network-on-chip

Inline ECC function for system-on-chip

Controlling exclusive access using supplemental transaction identifiers

Error protection for bus interconnect circuits

Programmable IC with safety sub-system

Circuits for and methods of providing isolation in an integrated circuit

Multi-use chip-to-chip interface

Systems and methods to transport memory mapped traffic amongst integrated circuit devices

Chip bump interface compatible with different orientations and types of devices

Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip

Auto-precharge management in a controller

Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip

Translation look-aside buffer prefetch initiated by bus master

Bridging inter-bus communications

Circuits for and methods of enabling the access to data

IC with adaptive chip-to-chip interface to support different chip-to-chip

Multi-use chip-to-chip interface

Chip bump interface compatible with different orientations and types of devices

Localized NoC switching interconnect for high bandwidth interfaces

NoC relaxed write order scheme

On-demand packetization for a chip-to-chip interface

Adaptive quality of service control circuit

Configurable network-on-chip for a programmable device

Integrated circuit transaction redundancy

Memory controller cryptographic data quantization using a cache

Interconnect circuitry for multi-channel and multi-requester memory systems

Memory controller to perform in-line data processing and efficiently organize data and associated metadata in memory

Network-on-chip architecture for handling different data sizes

System-on-chip having multiple circuits and memory controller in separate and independent power domains

Visualizing operation of a memory controller

Processing system display controller interface to programmable logic

Key management system

Processing system network controller with interface to programmable logic

DRAM controller with in-line ECC

Memory controller with reduced latency transaction scheduling

NAT SEMICONDUCTOR CORP

Programmable RISC-DSP architecture

Audio/video subprocessor method and structure

Method and apparatus for computing MPEG video reconstructed DCT coefficients

System and method for decoding audio/video data such as DVD or/and DVB data

ROLM CO

Method and apparatus for handling incoming telephone calls

Method and apparatus for sharing speakerphone processor among multiple users

IBM

Full-duplex digital speakerphone

Half-duplex speakerphone

BAY MICROSYSEMS INC

Switching network

LSI CORP

Fractional phase-locked loop for generating high-definition and standard-definition reference clocks

BAY MICROSYSTEMS INC

Hitless reconfiguration of a switching network