Inventor
FU CHU-YUN
TW46 patents
⚠️ This page may combine multiple inventors who share the name “FU CHU-YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
33 patentsUS6316348B1Nov 13, 2001
High selectivity Si-rich SiON etch-stop layer
TAIWAN SEMICONDUCTOR MFG175 citations99
US7612405B2Nov 3, 2009
Fabrication of FinFETs with multiple fin heights
TAIWAN SEMICONDUCTOR MFG55 citations98
US6214698B1Apr 10, 2001
Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
TAIWAN SEMICONDUCTOR MFG108 citations98
US7118987B2Oct 10, 2006
Method of achieving improved STI gap fill with reduced stress
TAIWAN SEMICONDUCTOR MFG109 citations97
US6245669B1Jun 12, 2001
High selectivity Si-rich SiON etch-stop layer
TAIWAN SEMICONDUCTOR MFG65 citations96
US6174808B1Jan 16, 2001
Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
TAIWAN SEMICONDUCTOR MFG55 citations96
US6174818B1Jan 16, 2001
Method of patterning narrow gate electrode
TAIWAN SEMICONDUCTOR MFG77 citations96
US7119404B2Oct 10, 2006
High performance strained channel MOSFETs by coupled stress effects
TAIWAN SEMICONDUCTOR MFG35 citations93
US6479385B1Nov 12, 2002
Interlevel dielectric composite layer for insulation of polysilicon and metal structures
TAIWAN SEMICONDUCTOR MFG25 citations93
US6444566B1Sep 3, 2002
Method of making borderless contact having a sion buffer layer
TAIWAN SEMICONDUCTOR MFG22 citations93
US6274514B1Aug 14, 2001
HDP-CVD method for forming passivation layers with enhanced adhesion
TAIWAN SEMICONDUCTOR MFG32 citations93
US6261957B1Jul 17, 2001
Self-planarized gap-filling by HDPCVD for shallow trench isolation
TAIWAN SEMICONDUCTOR MFG35 citations93
US6245682B1Jun 12, 2001
Removal of SiON ARC film after poly photo and etch
TAIWAN SEMICONDUCTOR MFG22 citations93
US6090714AJul 18, 2000
Chemical mechanical polish (CMP) planarizing trench fill method employing composite trench fill layer
TAIWAN SEMICONDUCTOR MFG34 citations93
US6063711AMay 16, 2000
High selectivity etching stop layer for damascene process
TAIWAN SEMICONDUCTOR MFG47 citations93
US6426272B1Jul 30, 2002
Method to reduce STI HDP-CVD USG deposition induced defects
TAIWAN SEMICONDUCTOR MFG24 citations92
US6884736B2Apr 26, 2005
Method of forming contact plug on silicide structure
TAIWAN SEMICONDUCTOR MFG20 citations91
US7371629B2May 13, 2008
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications
TAIWAN SEMICONDUCTOR MFG10 citations84
US6372664B1Apr 16, 2002
Crack resistant multi-layer dielectric layer and method for formation thereof
TAIWAN SEMICONDUCTOR MFG20 citations84
US9379215B2Jun 28, 2016
Fin field effect transistor
TAIWAN SEMICONDUCTOR MFG4 citations83
US9209300B2Dec 8, 2015
Fin field effect transistor
TAIWAN SEMICONDUCTOR MFG8 citations83
US8809940B2Aug 19, 2014
Fin held effect transistor
TAIWAN SEMICONDUCTOR MFG8 citations83
US7611963B1Nov 3, 2009
Method for forming a multi-layer shallow trench isolation structure in a semiconductor device
TAIWAN SEMICONDUCTOR MFG8 citations83
US6228780B1May 8, 2001
Non-shrinkable passivation scheme for metal em improvement
TAIWAN SEMICONDUCTOR MFG16 citations83
US6497993B1Dec 24, 2002
In situ dry etching procedure to form a borderless contact hole
TAIWAN SEMICONDUCTOR MFG19 citations81
US6423653B1Jul 23, 2002
Reduction of plasma damage for HDP-CVD PSG process
TAIWAN SEMICONDUCTOR MFG8 citations74
US6207483B1Mar 27, 2001
Method for smoothing polysilicon gate structures in CMOS devices
TAIWAN SEMICONDUCTOR MFG12 citations74
US7098116B2Aug 29, 2006
Shallow trench isolation method for reducing oxide thickness variations at different pattern densities
TAIWAN SEMICONDUCTOR MFG8 citations67
US6713406B1Mar 30, 2004
Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices
TAIWAN SEMICONDUCTOR MFG5 citations63
US6630398B2Oct 7, 2003
Borderless contact with buffer layer
TAIWAN SEMICONDUCTOR MFG3 citations63
US6461966B1Oct 8, 2002
Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement
TAIWAN SEMICONDUCTOR MFG5 citations55
US7297632B2Nov 20, 2007
Scratch reduction for chemical mechanical polishing
TAIWAN SEMICONDUCTOR MFG0 citations48
US7892909B2Feb 22, 2011
Polysilicon gate formation by in-situ doping
TAIWAN SEMICONDUCTOR MFG0 citations42
TAIWAN SEMICONDUCTOR MFG CO LTD
3 patentsUS9716091B2Jul 25, 2017
Fin field effect transistor
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations83
US10269616B2Apr 23, 2019
Method of fabricating semiconductor device isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US9673082B2Jun 6, 2017
Method of fabricating semiconductor device isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
YU CHEN-HUA
3 patentsUS8110890B2Feb 7, 2012
Method of fabricating semiconductor device isolation structure
YU CHEN-HUA2 citations63
US8822293B2Sep 2, 2014
Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
YU CHEN-HUA2 citations60
US9224606B2Dec 29, 2015
Method of fabricating semiconductor device isolation structure
YU CHEN-HUA0 citations52
TAIWAN SEMICONDUCTOR MAUFACTUR
2 patentsUS6037018AMar 14, 2000
Shallow trench isolation filled by high density plasma chemical vapor deposition
TAIWAN SEMICONDUCTOR MAUFACTUR378 citations98
US6365523B1Apr 2, 2002
Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers
TAIWAN SEMICONDUCTOR MAUFACTUR25 citations92