Inventor

MUSOLL ENRIQUE

US69 patents

⚠️ This page may combine multiple inventors who share the name “MUSOLL ENRIQUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUSOLL ENRIQUE

MIPS TECH INC

Fetch and dispatch disassociation apparatus for multistreaming processors

Clustering stream and/or instruction queues for multi-streaming processors

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

Method for allocating memory space for limited packet head and/or tail growth

Method and apparatus for non-speculative pre-fetch operation in data packet processing

Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing

Functional validation of a packet management unit

Method and apparatus for improved computer load and store operations

Method and apparatus for non-speculative pre-fetch operation in data packet processing

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

Method for allocating memory space for limited packet head and/or tail growth

Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory

Extended instruction set for packet processing applications

Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory

Fetch and dispatch disassociation apparatus for multistreaming processors

Fetch and dispatch disassociation apparatus for multi-streaming processors

Functional validation of a packet management unit

Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management

ASTERA LABS INC

Retimer with mesochronous intra-lane path controllers

Low-latency retimer with seamless clock switchover

Capacity-expanding memory control component

Early potential HPA generator

Capacity-expanding memory control component

Capacity-expanding memory control component

Low-latency retimer with seamless clock switchover

Low-latency signaling-link retimer

Early potential HPA generator

Capacity-expanding memory control component

Configurable-aggregation retimer with lane-dedicated controllers

Retimer with path-coordinated flow-rate compensation

Low-latency retimer with seamless clock switchover

Low-latency signaling-link retimer

Retimer with mesochronous intra-lane path controllers

Retimer with path-coordinated flow-rate compensation

MARVELL ASIA PTE LTD

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device utilizing a port client chain

Packet processing system, method and device having reduced static power consumption

Packet processing system, method and device utilizing a port client chain

CONSENTRY NETWORKS INC

Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory

Monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads

Multi-threaded packet processing engine for stateful packet processing

NAT SEMICONDUCTOR CORP

Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches

MUSOLL ENRIQUE

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

CAVIUM LLC

Packet processing system, method and device having reduced static power consumption