Inventor
NEMIROVSKY MARIO
US43 patents
⚠️ This page may combine multiple inventors who share the name “NEMIROVSKY MARIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
24 patentsUS7257814B1Aug 14, 2007
Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
MIPS TECH INC99 citations98
US7032226B1Apr 18, 2006
Methods and apparatus for managing a buffer of events in the background
MIPS TECH INC69 citations97
US7139898B1Nov 21, 2006
Fetch and dispatch disassociation apparatus for multistreaming processors
MIPS TECH INC44 citations96
US7035997B1Apr 25, 2006
Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
MIPS TECH INC61 citations96
US7035998B1Apr 25, 2006
Clustering stream and/or instruction queues for multi-streaming processors
MIPS TECH INC68 citations94
US7502876B1Mar 10, 2009
Background memory manager that determines if data structures fits in memory with memory state transactions map
MIPS TECH INC49 citations92
US7237093B1Jun 26, 2007
Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
MIPS TECH INC20 citations92
US7165257B2Jan 16, 2007
Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
MIPS TECH INC29 citations92
US7065096B2Jun 20, 2006
Method for allocating memory space for limited packet head and/or tail growth
MIPS TECH INC24 citations92
US7058064B2Jun 6, 2006
Queueing system for processors in packet routing operations
MIPS TECH INC23 citations92
US7042887B2May 9, 2006
Method and apparatus for non-speculative pre-fetch operation in data packet processing
MIPS TECH INC23 citations92
US7058065B2Jun 6, 2006
Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
MIPS TECH INC45 citations90
US7043467B1May 9, 2006
Wire-speed multi-dimensional packet classifier
MIPS TECH INC21 citations88
US7649901B2Jan 19, 2010
Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
MIPS TECH INC9 citations84
US7280548B2Oct 9, 2007
Method and apparatus for non-speculative pre-fetch operation in data packet processing
MIPS TECH INC12 citations83
US7197043B2Mar 27, 2007
Method for allocating memory space for limited packet head and/or tail growth
MIPS TECH INC6 citations74
US7155516B2Dec 26, 2006
Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
MIPS TECH INC6 citations74
US7139901B2Nov 21, 2006
Extended instruction set for packet processing applications
MIPS TECH INC9 citations74
US7715410B2May 11, 2010
Queueing system for processors in packet routing operations
MIPS TECH INC6 citations73
US7661112B2Feb 9, 2010
Methods and apparatus for managing a buffer of events in the background
MIPS TECH INC5 citations73
US7877481B2Jan 25, 2011
Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
MIPS TECH INC5 citations63
US7406586B2Jul 29, 2008
Fetch and dispatch disassociation apparatus for multi-streaming processors
MIPS TECH INC4 citations63
US7076630B2Jul 11, 2006
Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
MIPS TECH INC2 citations63
US7551626B2Jun 23, 2009
Queueing system for processors in packet routing operations
MIPS TECH INC4 citations62
NAT SEMICONDUCTOR CORP
7 patentsUS6237074B1May 22, 2001
Tagged prefetch and instruction decoder for variable length instruction set and method of operation
NAT SEMICONDUCTOR CORP72 citations96
US5680564AOct 21, 1997
Pipelined processor with two tier prefetch buffer structure and method with bypass
NAT SEMICONDUCTOR CORP69 citations94
US5752273AMay 12, 1998
Apparatus and method for efficiently determining addresses for misaligned data stored in memory
NAT SEMICONDUCTOR CORP27 citations91
US5692146ANov 25, 1997
Method of implementing fast 486TM microprocessor compatible string operations
NAT SEMICONDUCTOR CORP24 citations91
US6105125AAug 15, 2000
High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information
NAT SEMICONDUCTOR CORP24 citations86
US5655139AAug 5, 1997
Execution unit architecture to support X86 instruction set and X86 segmented addressing
NAT SEMICONDUCTOR CORP10 citations69
US5649147AJul 15, 1997
Circuit for designating instruction pointers for use by a processor decoder
NAT SEMICONDUCTOR CORP1 citations52
MIRAVEO INC
3 patentsUS10404572B1Sep 3, 2019
Communication between nodes in spontaneous area networks
MIRAVEO INC10 citations79
US9191303B2Nov 17, 2015
Systems and methods for creating, managing and communicating users and applications on spontaneous area networks
MIRAVEO INC5 citations79
US9794162B2Oct 17, 2017
Systems and methods for creating, managing and communicating users and applications on spontaneous area networks
MIRAVEO INC1 citations58
MOTOROLA INC
2 patentsCONSENTRY NETWORKS INC
2 patentsUS7634622B1Dec 15, 2009
Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory
CONSENTRY NETWORKS INC36 citations90
US7571270B1Aug 4, 2009
Monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads
CONSENTRY NETWORKS INC23 citations90