Inventor
MELVIN STEPHEN
US16 patents
⚠️ This page may combine multiple inventors who share the name “MELVIN STEPHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
15 patentsUS7257814B1Aug 14, 2007
Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
MIPS TECH INC99 citations98
US7165257B2Jan 16, 2007
Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
MIPS TECH INC29 citations92
US7065096B2Jun 20, 2006
Method for allocating memory space for limited packet head and/or tail growth
MIPS TECH INC24 citations92
US7058064B2Jun 6, 2006
Queueing system for processors in packet routing operations
MIPS TECH INC23 citations92
US7042887B2May 9, 2006
Method and apparatus for non-speculative pre-fetch operation in data packet processing
MIPS TECH INC23 citations92
US7765554B2Jul 27, 2010
Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
MIPS TECH INC12 citations84
US7529907B2May 5, 2009
Method and apparatus for improved computer load and store operations
MIPS TECH INC12 citations84
US7280548B2Oct 9, 2007
Method and apparatus for non-speculative pre-fetch operation in data packet processing
MIPS TECH INC12 citations83
US7197043B2Mar 27, 2007
Method for allocating memory space for limited packet head and/or tail growth
MIPS TECH INC6 citations74
US7155516B2Dec 26, 2006
Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
MIPS TECH INC6 citations74
US7139901B2Nov 21, 2006
Extended instruction set for packet processing applications
MIPS TECH INC9 citations74
US7715410B2May 11, 2010
Queueing system for processors in packet routing operations
MIPS TECH INC6 citations73
US7650605B2Jan 19, 2010
Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
MIPS TECH INC7 citations73
US7877481B2Jan 25, 2011
Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
MIPS TECH INC5 citations63
US7551626B2Jun 23, 2009
Queueing system for processors in packet routing operations
MIPS TECH INC4 citations62