Inventor

WILLIAMS RICHARD Q

US67 patents

⚠️ This page may combine multiple inventors who share the name “WILLIAMS RICHARD Q”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILLIAMS RICHARD Q

IBM

FET channel having a strained lattice structure along multiple surfaces

Chip interconnection structure using stub terminals

Dynamic control of back gate bias in a FinFET SRAM cell

Chip edge interconnect apparatus and method

Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application

Method and apparatus for interconnecting multiple circuit chips

Nonvolatile memory cell using microelectromechanical device

Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models

Apparatus and method for antifuse with electrostatic assist

ESD network with capacitor blocking element

Curved FINFETs

Doped single crystal silicon silicided eFuse

Discrete on-chip SOI resistors

Method for making a FET channel

Structure and method for dual-gate FET with SOI substrate

Antifuse with electrostatic assist

NVRAM array device with enhanced write and erase

Method and apparatus for providing electrostatic discharge protection

NVRAM utilizing high voltage TFT device and method for making the same

Carbon nanotube based integrated semiconductor circuit

Structure for reduced source and drain contact to gate stack capacitance

Structure for reduced source and drain contact to gate stack capacitance

Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure

Carbon nanotube based integrated semiconductor circuit

Semiconductor device stress modeling methodology

Chip-in-slot interconnect for 3D chip stacks

FETS with self-aligned bodies and backgate holes

Semiconductor devices having torsional stresses

Structure and method for dual-gate FET with SOI substrate

Apparatus and method for detecting defective NVRAM cells

System and methodology for determining layout-dependent effects in ULSI simulation

Method for soft error modeling with double current pulse

Method and apparatus for improving SRAM cell stability by using boosted word lines

High performance capacitors in planar back gates CMOS

Doped single crystal silicon silicided eFuse

Structure for reduced source and drain contact to gate stack capacitance

Modeling transistor performance considering non-uniform local layout effects

Semispherical integrated circuit structures

Integrated circuit (IC) with high-Q on-chip discrete capacitors

Structure and method for mixed-substrate SIMOX technology

Epitaxial imprinting

Structure and method for thin box SOI device

Apparatus for modeling of FinFET width quantization

Methods for modeling of FinFET width quantization

FURUKAWA TOSHIHARU

Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure

APPENZELLER JOERG

Carbon nanotube based integrated semiconductor circuit

LI HONGMEI

Analysis of compensated layout shapes

CHIDAMBARRAO DURESETI

Circuit analysis using transverse buckets

BERNSTEIN KERRY

System and method for target-based compact modeling

BRYANT ANDRES

High performance capacitors in planar back gates CMOS