Inventor

HOFMANN RICHARD G

US23 patents

⚠️ This page may combine multiple inventors who share the name “HOFMANN RICHARD G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOFMANN RICHARD G

IBM

Arbitration logic for multiple bus computer system

System direct memory access (DMA) support logic for PCI based computer system

Dynamic bus sizing of DMA transfers

Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management

Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller

Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration

System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration

Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension

Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels

Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses

Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer

Bridge for a power managed computer system with multiple buses and system arbitration

Error detection and recovery in a DMA controller

Method and apparatus for bus access allocation

Transfer request pipeline throttling

Reducing snoop response time for snoopers without copies of requested data via snoop filtering

Reducing latency of a snoop tenure

Single request data transfer regardless of size and alignment

Selective snooping by snoop masters to locate updated data

Selective snooping by snoop masters to locate updated data

Single request data transfer regardless of size and alignment

INTEL CORP

Power management of DMA slaves with DMA traps

SHIRLEN MARTYN R

Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus