Inventor

MO RENEE T

US87 patents

⚠️ This page may combine multiple inventors who share the name “MO RENEE T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MO RENEE T

IBM

Ultra-thin body super-steep retrograde well (SSRW) FET devices

Test structure for detection of gap in conductive layer of multilayer gate stack

Extremely-thin silicon-on-insulator transistor with raised source/drain

Chemical treatment to retard diffusion in a semiconductor overlayer

Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

Extremely-thin silicon-on-insulator transistor with raised source/drain

Semiconductor device having a strained raised source/drain

Patterned gate dielectrics for III-V-based CMOS circuits

III-V lateral bipolar integration with silicon

Semiconductor structure with integrated passive structures

Automatic defect detection and classification for high throughput electron channeling contrast imaging

Method of forming high-germanium content silicon germanium alloy fins on insulator

Dual-semiconductor complementary metal-oxide-semiconductor device

High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods

Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same

Method for tuning the threshold voltage of a metal gate and high-k device

Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

Nitrogen based plasma process for metal gate MOS device

Method and process for forming a self-aligned silicide contact

Method for forming self-aligned metal silicide contacts

Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor

Metal high-k transistor having silicon sidewall for reduced parasitic capacitance

Method for forming self-aligned metal silicide contacts

Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap

Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers

Patterned gate dielectrics for III-V-based CMOS circuits

DNA sequencing detection field effect transistor

Asymmetric III-V MOSFET on silicon substrate

III-V compound semiconductor channel material formation on mandrel after middle-of-the-line dielectric formation

Dual-semiconductor complementary metal-oxide-semiconductor device

Asymmetric III-V MOSFET on silicon substrate

Integrated circuit having local maximum operating voltage

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process

Semiconductor structure with integrated passive structures

High-K metal gate CMOS

Electroless metal deposition for dual work function

Forming shallow trench isolation without the use of CMP

III-V CMOS co-integration

MO RENEE T

Test structure for detection of gap in conductive layer of multilayer gate stack

High-k/metal gate transistor with L-shaped gate encapsulation layer

LIU YAOCHENG

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

CHANG JOSEPHINE B

Multiple Vt field-effect transistor devices

Multiple Vt field-effect transistor devices

CHANG LELAND

Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance

CABRAL JR CYRIL

Method and process for forming a self-aligned silicide contact

GLOBALFOUNDRIES INC

Epitaxial growth of material on source/drain regions of FinFET structure

CHUDZIK MICHAEL P

High-K dielectric and metal gate stack with minimal overlap with isolation region