Inventor
STRANE JAY W
US28 patents
⚠️ This page may combine multiple inventors who share the name “STRANE JAY W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
23 patentsUS7041571B2May 9, 2006
Air gap interconnect structure and method of manufacture
IBM73 citations97
US9666474B2May 30, 2017
Uniform dielectric recess depth during fin reveal
IBM5 citations84
US6989317B1Jan 24, 2006
Trench formation in semiconductor integrated circuits (ICs)
IBM19 citations84
US7544610B2Jun 9, 2009
Method and process for forming a self-aligned silicide contact
IBM14 citations82
US6887785B1May 3, 2005
Etching openings of different depths using a single mask layer method and structure
IBM17 citations82
US8039382B2Oct 18, 2011
Method for forming self-aligned metal silicide contacts
IBM6 citations74
US7618891B2Nov 17, 2009
Method for forming self-aligned metal silicide contacts
IBM6 citations74
US6809027B2Oct 26, 2004
Self-aligned borderless contacts
IBM12 citations74
US6806177B2Oct 19, 2004
Method of making self-aligned borderless contacts
IBM10 citations74
US11189532B2Nov 30, 2021
Dual width finned semiconductor structure
IBM0 citations63
US9984935B2May 29, 2018
Uniform dielectric recess depth during fin reveal
IBM1 citations63
US11043429B2Jun 22, 2021
Semiconductor fins with dielectric isolation at fin bottom
IBM0 citations62
US10636709B2Apr 28, 2020
Semiconductor fins with dielectric isolation at fin bottom
IBM1 citations62
US10535550B2Jan 14, 2020
Protection of low temperature isolation fill
IBM1 citations62
US7790553B2Sep 7, 2010
Methods for forming high performance gates and structures thereof
IBM5 citations62
US10892193B2Jan 12, 2021
Controlling active fin height of FinFET device
IBM0 citations60
US10672668B2Jun 2, 2020
Dual width finned semiconductor structure
IBM0 citations52
US10586700B2Mar 10, 2020
Protection of low temperature isolation fill
IBM0 citations52
US9984916B2May 29, 2018
Uniform dielectric recess depth during fin reveal
IBM0 citations52
US9941134B2Apr 10, 2018
Uniform dielectric recess depth during fin reveal
IBM0 citations52
US10770361B2Sep 8, 2020
Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
IBM0 citations49
US10665514B2May 26, 2020
Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
IBM0 citations49
US6960306B2Nov 1, 2005
Low Cu percentages for reducing shorts in AlCu lines
IBM0 citations44