P

Inventor

SUNDLOF BRIAN R

US36 patents
⚠️ This page may combine multiple inventors who share the name “SUNDLOF BRIAN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

28 patents
US7351360B2Apr 1, 2008

Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive

IBM33 citations96
US7611923B2Nov 3, 2009

Method and apparatus for forming stacked die and substrate structures for increased packing density

IBM17 citations92
US7250675B2Jul 31, 2007

Method and apparatus for forming stacked die and substrate structures for increased packing density

IBM19 citations92
US11244917B2Feb 8, 2022

Multilayer pillar for reduced stress interconnect and method of making same

IBM4 citations84
US10403590B2Sep 3, 2019

Multilayer pillar for reduced stress interconnect and method of making same

IBM4 citations84
US10396051B2Aug 27, 2019

Multilayer pillar for reduced stress interconnect and method of making same

IBM3 citations84
US7449067B2Nov 11, 2008

Method and apparatus for filling vias

IBM12 citations82
US10622299B2Apr 14, 2020

Multi terminal capacitor within input output path of semiconductor package interconnect

IBM1 citations73
US9947598B1Apr 17, 2018

Determining crackstop strength of integrated circuit assembly at the wafer level

IBM3 citations73
US9018760B2Apr 28, 2015

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

IBM2 citations63
US7708909B2May 4, 2010

Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive

IBM2 citations63
US7288474B2Oct 30, 2007

Suspension for filling via holes in silicon and method for making the same

IBM4 citations63
US11171102B2Nov 9, 2021

Multilayer pillar for reduced stress interconnect and method of making same

IBM0 citations62
US11094657B2Aug 17, 2021

Multilayer pillar for reduced stress interconnect and method of making same

IBM0 citations62
US7294909B2Nov 13, 2007

Electronic package repair process

IBM2 citations60
US6823585B2Nov 30, 2004

Method of selective plating on a substrate

IBM2 citations60
US10224274B2Mar 5, 2019

Multi terminal capacitor within input output path of semiconductor package interconnect

IBM0 citations52
US10224273B2Mar 5, 2019

Multi terminal capacitor within input output path of semiconductor package interconnect

IBM0 citations52
US9899313B2Feb 20, 2018

Multi terminal capacitor within input output path of semiconductor package interconnect

IBM0 citations52
US9640501B2May 2, 2017

Multilayer pillar for reduced stress interconnect and method of making same

IBM0 citations52
US9263363B2Feb 16, 2016

Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive

IBM0 citations52
US7202154B2Apr 10, 2007

Suspension for filling via holes in silicon and method for making the same

IBM1 citations52
US8910853B2Dec 16, 2014

Additives for grain fragmentation in Pb-free Sn-based solder

IBM0 citations51
US7897878B2Mar 1, 2011

Compliant penetrating packaging interconnect

IBM0 citations51
US7784669B2Aug 31, 2010

Method and process for reducing undercooling in a lead-free tin-rich solder alloy

IBM1 citations49
US7703661B2Apr 27, 2010

Method and process for reducing undercooling in a lead-free tin-rich solder alloy

IBM1 citations49
US6916670B2Jul 12, 2005

Electronic package repair process

IBM1 citations49
US7683493B2Mar 23, 2010

Intermetallic diffusion block device and method of manufacture

IBM0 citations46

JADHAV VIRENDRA R

3 patents

ARVIN CHARLES L

2 patents

HOUGHAM GARETH

2 patents

BUSBY JAMES A

1 patent