Inventor

PAN SHING-CHYANG

TW57 patents

⚠️ This page may combine multiple inventors who share the name “PAN SHING-CHYANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN SHING-CHYANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-patterning to form vias with straight profiles

Manufacturing method of semiconductor device

Etch stop layer for semiconductor devices

Metal-based etch-stop layer

Via structure, MRAM device using the via structure and method for fabricating the MRAM device

Etch stop layer for semiconductor devices

Physical vapor deposition chamber with target surface morphology monitor

Etch stop layer for semiconductor devices

Multi-patterning to form vias with straight profiles

Metal-based etch-stop layer

Systems and methods for integrated resputtering in a physical vapor deposition chamber

Plasma apparatus, magnetic-field controlling method, and semiconductor manufacturing method

Memory device and method for fabricating the same

Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature

Morphology of resist mask prior to etching

Patterning methods for semiconductor devices

Memory device

Method for manufacturing a semiconductor device

High aspect ratio gap fill

Physical vapor deposition chamber with target surface morphology monitor

Method for manufacturing a semiconductor device

Etch stop layer for semiconductor devices

Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure

Memory device and method for fabricating the same

Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure

Metal-based etch-stop layer

Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature

Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure

Patterning methods for semiconductor devices

Patterning methods for semiconductor devices

Diffusion barrier layer in programmable metallization cell

Diffusion barrier layer in programmable metallization cell

Diffusion barrier layer in programmable metallization cell

Systems and methods for integrated resputtering in a physical vapor deposition chamber

Multi-patterning to form vias with straight profiles

Manufacturing method of semiconductor device

Surface pre-treatment for hard mask fabrication

TAIWAN SEMICONDUCTOR MFG

Barrier layer for copper interconnect

Barrier structure for semiconductor devices

Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers

Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer

Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties

Multi-step Cu seed layer formation for improving sidewall coverage

Method of avoiding plasma arcing during RIE etching

High performance metallization cap layer

Method for simultaneous degas and baking in copper damascene process

System and method for film stress and curvature gradient mapping for screening problematic wafers

Composite barrier layer

Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers

SU LI-LIN

In situ Cu seed layer formation for improving sidewall coverage