Inventor

LUNDBERG JAMES R

US87 patents

⚠️ This page may combine multiple inventors who share the name “LUNDBERG JAMES R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUNDBERG JAMES R

VIA TECH INC

Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout

Sense mechanism for microprocessor bus inversion

Digital power gating with programmable control parameter

Fast dynamic register

Apparatus and method for locking out a source synchronous strobe receiver

Apparatus and method for enabling a multi-processor environment on a bus

Dynamic logic register

P-domino output latch with accelerated evaluate path

Microprocessor with selective substrate biasing for clock-gated functional blocks

N-domino output latch

P-domino output latch

Overvoltage protection apparatus

Digital power gating with state retention

Apparatus and method for generating a clock signal with reduced jitter

Apparatus and method for automatically aligning data signals and strobe signals on a source synchronous bus

Apparatus and method for automatically aligning data signals and strobe signals on a source synchronious bus

Source synchronous bus signal alignment compensation mechanism

IP FIRST LLC

Random number generator with selectable dual random bit string engines

Apparatus and method for adjusting the impedance of an output driver

Thin gate oxide output drive

Integrated circuit timing debug apparatus and method

Apparatus for generating random numbers

Slew-controlled split-voltage output driver

Multiple mode clock receiver

Dynamic logic return-to-zero latching mechanism

Dynamic logic register

Digital level shifter for maintaining gate oxide integrity of scaled driver devices

Oscillator bias variation mechanism

MOTOROLA INC

Method and apparatus for performing frequency detection

Output circuit for interfacing integrated circuits having different power supply potentials

Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation

Power reduction method and apparatus for phase-locked loop based clocks in a data processing system

Method and apparatus for power-up state initialization in a data processing system

Method and apparatus for performing phase acquisition in an all digital phase lock loop

Method and apparatus for determining a constant gain of a variable oscillator

Method and apparatus for performing frequency tracking in an all digital phase lock loop

Method and apparatus for performing frequency acquisition in all digital phase lock loop

DIGITAL EQUIPMENT CORP

State machine phase lock loop

Low-voltage CMOS output buffer

High-speed, low-noise, CMOS output driver

Reduced-voltage NMOS output driver

(unassigned)

Multi-level game board apparatus

Multi-level game board

INTEGRATED DEVICE TECH

Test ring oscillator

Configurable drive clock

VIA ALLIANCE SEMICONDUCTOR CO LTD

Data synchronizer for latching an asynchronous data signal relative to a clock signal

Scannable data synchronizer

GASKINS DARIUS D

Configurable bus termination for multi-core/multi-package processor configurations

CENTAUR TECH INC

Fast precision droop detector

LUNDBERG JAMES R

Registers with reduced voltage clocks