Inventor

KUMAR PROMOD

IN38 patents

⚠️ This page may combine multiple inventors who share the name “KUMAR PROMOD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUMAR PROMOD

ST MICROELECTRONICS INT NV

Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

In-memory computation circuit using static random access memory (SRAM) array segmentation

Bit-cell architecture based in-memory compute

SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications

Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current

Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

At-speed transition fault testing for a multi-port and multi-clock memory

Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection

Built-in self test circuit for segmented static random access memory (SRAM) array input/output

Modular memory architecture with gated sub-array operation dependent on stored data content

ST MICROELECTRONICS SRL

Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode

Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data

Stabilized delay circuit

Redundancy architecture for an interleaved memory

Memory test method and nonvolatile memory with low error masking probability

Built-in testing methodology in flash memory

Nonvolatile memory and high speed memory test method

Circuit for managing the transfer of data streams from a plurality of sources within a system

Computing system power management device, system and method

Computing system power management device, system and method

ATD generation in a synchronous memory

Accelerated carry generation

CHAWLA NITIN

Fail safe adaptive voltage/frequency system

Fail safe adaptive voltage/frequency system

TANDON AMIT

Fail-safe high speed level shifter for wide supply voltage range

ELECTRIC POWER RES INST

Preparation of Bi-Pb-Sr-Ca-Cu-O (2223) superconductors

STMICROELECTONICS S R L

Interleaved memory device for sequential access synchronous reading with simplified address counters

GILLETTE CO

Non-aerosol Shaving gel free of thickening and gelling agents

ST MICROELECTRONICS PVT LTD

High voltage switch with reduced voltage stress at output stage

TEXAS INSTRUMENTS INC

Method of fabricating a dynamic random access memory with increased capacitance

STMICROELECTRONICS FRANCE

Silicon-on-insulator semiconductor device with a static random access memory circuit

AUST DUNCAN T

Water-in-oil emulsion compositions containing gellan gum for topical delivery of active ingredients to the skin or mucosa