Inventor
DERR MICHAEL N
US31 patents
⚠️ This page may combine multiple inventors who share the name “DERR MICHAEL N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
27 patentsUS7523327B2Apr 21, 2009
System and method of coherent data transfer during processor idle states
INTEL CORP19 citations92
US6779062B1Aug 17, 2004
Streamlining ATA device initialization
INTEL CORP17 citations91
US7340550B2Mar 4, 2008
USB schedule prefetcher for low power
INTEL CORP19 citations90
US7296101B2Nov 13, 2007
Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device
INTEL CORP19 citations89
US9189046B2Nov 17, 2015
Performing cross-domain thermal control in a processor
INTEL CORP6 citations83
US6453375B1Sep 17, 2002
Method and apparatus for obtaining coherent accesses with posted writes from multiple software drivers
INTEL CORP7 citations73
US5893917AApr 13, 1999
Memory controller and method of closing a page of system memory
INTEL CORP13 citations73
US7093115B2Aug 15, 2006
Method and apparatus for detecting an interruption in memory initialization
INTEL CORP8 citations71
US6775282B1Aug 10, 2004
Bus communication
INTEL CORP12 citations71
US9423858B2Aug 23, 2016
Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain
INTEL CORP3 citations64
US7822978B2Oct 26, 2010
Quiescing a manageability engine
INTEL CORP2 citations63
US6275887B1Aug 14, 2001
Method and apparatus for terminating a bus transaction if the target is not ready
INTEL CORP6 citations62
US9195292B2Nov 24, 2015
Controlling reduced power states using platform latency tolerance
INTEL CORP2 citations61
US10643573B2May 5, 2020
Technologies for end-to-end display integrity verification for functional safety
INTEL CORP1 citations60
US8347015B2Jan 1, 2013
Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates
INTEL CORP2 citations60
US10678623B2Jun 9, 2020
Error reporting and handling using a common error handler
INTEL CORP1 citations59
US11043158B2Jun 22, 2021
Video bandwidth optimization for multi-monitor systems
INTEL CORP0 citations57
US7636795B2Dec 22, 2009
Configurable feature selection mechanism
INTEL CORP3 citations56
US7694004B2Apr 6, 2010
Bit-granular writes of control registers
INTEL CORP1 citations52
US9541983B2Jan 10, 2017
Controlling reduced power states using platform latency tolerance
INTEL CORP0 citations51
US6957280B2Oct 18, 2005
Streamlining ATA device initialization
INTEL CORP1 citations51
US10387993B2Aug 20, 2019
Fault-tolerant graphics display engine
INTEL CORP0 citations50
US12461585B2Nov 4, 2025
Granular GPU DVFS with execution unit partial powerdown
INTEL CORP0 citations49
US12437355B2Oct 7, 2025
Granular GPU DVFS with execution unit partial powerdown
INTEL CORP0 citations49
US7712145B2May 4, 2010
Chipset configuration authentication via manageability engine
INTEL CORP0 citations48
US11544160B2Jan 3, 2023
IPS SOC PLL monitoring and error reporting
INTEL CORP0 citations42
US10749547B2Aug 18, 2020
Error detector and/or corrector checker method and apparatus
INTEL CORP0 citations39