Inventor

JACOBSON QUINN A

US53 patents

⚠️ This page may combine multiple inventors who share the name “JACOBSON QUINN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JACOBSON QUINN A

SUN MICROSYSTEMS INC

Method and apparatus for releasing memory locations during transactional execution

Selectively monitoring loads to support transactional program execution

Method and apparatus for delaying interfering accesses from other threads during transactional program execution

Method and apparatus for avoiding locks by speculatively executing critical sections

Selectively unmarking load-marked cache lines during transactional program execution

Patchable and/or programmable pre-decode

Selectively unmarking load-marked cache lines during transactional program execution

Method for reducing lock manipulation overhead during access to critical code sections

Method and apparatus for supporting one or more servers on a single semiconductor chip

Backing Register File for processors

Logging of level-two cache transactions into banks of the level-two cache for system rollback

Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution

Selectively monitoring stores to support transactional program execution

Translating loads for accelerating virtualized partition

Method and apparatus for providing error correction within a register file of a CPU

Explicitly clustered register file and execution unit architecture

Multiple contexts for efficient use of translation lookaside buffer

Centralized BIST engine for testing on-chip memory structures

Patchable and/or programmable decode using predecode selection

Logically partitioning different classes of TLB entries within a single caching structure

Method and apparatus for facilitating a fast restart after speculative execution

Method and apparatus for providing fault-tolerance for temporary results within a CPU

Working register file entries with instruction based lifetime

Start transactional execution (STE) instruction to support transactional program execution

Fail instruction to support transactional program execution

INTEL CORP

Primitives to enhance thread-level speculation

Multithreading processor with thread predictor

Hardware acceleration for a software transactional memory system

Hardware acceleration for a software transactional memory system

Protecting memory by containing pointer accesses

Obscuring memory access patterns

Technique for thread communication and synchronization

Providing application-level information for use in cache management

Technique for using memory attributes

Handling precompiled binaries in a hardware accelerated software transactional memory system

ORACLE AMERICA INC

Selectively monitoring stores to support transactional program execution

Selectively monitoring loads to support transactional program execution

Return address stack recovery in a speculative execution computing apparatus

Method and structure for explicit software control using scoreboard status information

VIBRADO TECH INC

Arm sleeve for training

System and method for calibrating inertial measurement units

Method and system for tracking scores made by a player

Method and system for processing a video recording with sensor data

SAULSBURY ASHLEY

Method and message handling hardware structure for virtualization and isolation of partitions

Method and message handling hardware structure for virtualization and isolation of partitions

CHAUDHRY SHAILENDER

Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps

Logical power throttling of instruction decode rate for successive time periods

SAHA BRATIN

Concurrent thread execution using user-level asynchronous signaling

JACOBSON QUINN A

Primitives to enhance thread-level speculation

BUXTON MARK

Obscuring memory access patterns