Inventor
SURANA NEELAM
IN5 patents
Patents
5 patentsUS12068024B2Aug 20, 2024
Address dependent wordline timing in asynchronous static random access memory
CEREMORPHIC INC0 citations59
US11971448B2Apr 30, 2024
Process for scan chain in a memory
CEREMORPHIC INC0 citations57
US11693056B1Jul 4, 2023
Scan chain for memory with reduced power consumption
CEREMORPHIC INC1 citations57
US11935587B2Mar 19, 2024
Dynamic adjustment of wordline timing in static random access memory
CEREMORPHIC INC0 citations56
US11862282B2Jan 2, 2024
One transistor memory bitcell with arithmetic capability
CEREMORPHIC INC0 citations46