Inventor

SHEAFFER GAD

IL58 patents

⚠️ This page may combine multiple inventors who share the name “SHEAFFER GAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEAFFER GAD

INTEL CORP

Mechanisms to accelerate transactions using buffered stores

Method and apparatus for merging binary translated basic blocks of instructions

Mechanism to exploit synchronization overhead to improve multithreaded performance

N-wide add-compare-select instruction

Performing mode switching in an unbounded transactional memory (UTM) system

Protected cache architecture and secure programming paradigm to protect applications

Selective hardware lock disabling

Mechanisms to accelerate transactions using buffered stores

Mechanisms to accelerate transactions using buffered stores

Variable width, at least six-way addition/accumulation instructions

Addressing mode and/or instruction for providing sine and cosine value pairs

Multi-way select instructions using accumulated condition codes

Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Selective hardware lock disabling

Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Obscuring memory access patterns in conjunction with deadlock detection or avoidance

SHEAFFER GAD

Registering a user-handler in hardware for transactional memory event handling

Metaphysical address space for holding lossy metadata in hardware

Extending cache coherency protocols to support locally buffered data

Read and write monitoring attributes in transactional memory (TM) systems

Read and write monitoring attributes in transactional memory (TM) systems

Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

Memory model for hardware attributes within a transactional memory system

Memory model for hardware attributes within a transactional memory system

GRAY JAN

Performing mode switching in an unbounded transactional memory (UTM) system

Private memory regions and coherence optimizations

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

Wait loss synchronization

YAMADA KOICHI

Operating system virtual memory management for hardware transactional memory

Operating system virtual memory management for hardware transactional memory

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

ADL-TABATABAI ALI-REZA

Mechanisms to accelerate transactions using buffered stores

Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata

Software filtering in a transactional memory system

TAILLEFER MARTIN

Debugging mechanisms in a cache-based memory isolation system

Leveraging memory isolation hardware technology to efficiently detect race conditions

Instrumentation of hardware assisted transactional memory system

RAIKIN SHLOMO

Live lock free priority scheme for memory transactions in transactional memory

Protecting private data from cache attacks

MICROSOFT CORP

Metaphysically addressed cache metadata

Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers

GUERON SHAY

Obscuring memory access patterns in conjunction with deadlock detection or avoidance

SAHA BRATIN

Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM

MICROSOFT TECHNOLOGY LICENSING LLC

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

GABOR RON

Acceleration threads on idle OS-visible thread execution units

UR SHMUEL

Digital relay for out of network devices

WANG HONG

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

LEVANONI YOSSEFF

Accelerating unbounded memory transactions using nested cache resident transactions