Inventor

KU YOUNG-JUN

KR52 patents

⚠️ This page may combine multiple inventors who share the name “KU YOUNG-JUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KU YOUNG-JUN

SK HYNIX INC

Semiconductor device including multiple-input shift register circuit

Input/output (I/O) line test device and method for controlling the same

Semiconductor memory device including stacked memory chips

Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths

Semiconductor memory apparatus

Semiconductor apparatus capable of preventing refresh error and memory system using the same

Semiconductor memory device and method for operating the same

Semiconductor memory device

Stacked semiconductor device and semiconductor system including the same

Data input circuit and memory device including the same

Semiconductor apparatus, memory system and repair method thereof

Buffer circuit, semiconductor integrated circuit, and system including the buffer circuit

Semiconductor apparatus capable of preventing refresh error and memory system using the same

Strobe signal generation circuit and semiconductor apparatus using the same

Stacked semiconductor package

Semiconductor device and semiconductor system having the same

Semiconductor apparatus and test device therefor

Semiconductor memory device

Semiconductor device, semiconductor system including the same, and method for operating the same

Delay locked loop and data reception of a semiconductor apparatus

Semiconductor device

Stacked memory device and test method thereof

Semiconductor memory apparatus

Semiconductor apparatus and system capable of reducing peak current in transmitting signals

HYNIX SEMICONDUCTOR INC

Delay locked loop and semiconductor memory device with the same

Semiconductor device and delay locked loop circuit thereof

Duty cycle corrector and clock generator having the same

Register controlled delay locked loop circuit

Delay locked loop

Circuit and method for parallel test of memory device

Delay locked loop circuit and synchronous memory device including the same

Delayed locked loop circuit

Delay locked loop in synchronous semiconductor memory device and driving method thereof

Apparatus for generating internal voltage

Delayed Locked Loop Circuit

Data transmission circuit and semiconductor apparatus including the same

Delay locked loop circuit and operational method thereof

Delay locked loop circuit

Semiconductor memory device capable of effectively testing failure of data

Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line

Delay locked loop and semiconductor memory device with the same

Semiconductor memory device and method for driving the same

KU YOUNG-JUN

Semiconductor integrated circuit having stacked semiconductor chips and vias therebetween

Semiconductor memory device

Delay locked loop

KU YOUNG JUN

Semiconductor integrated circuit with testing and repairing via

Data transmission device

CHOI MIN SEOK

Repair circuit and semiconductor apparatus including the same

YUN TAE SIK

Three-dimensional stacked semiconductor integrated circuit

AHN JEONG-YOON

Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line