Inventor

BOLOTOV ANATOLI A

US43 patents

⚠️ This page may combine multiple inventors who share the name “BOLOTOV ANATOLI A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOLOTOV ANATOLI A

LSI LOGIC CORP

Fast free memory address controller

FIFO memory with single port memory modules for allowing simultaneous read and write operations

Integrated circuit and process for identifying minimum or maximum input value among plural inputs

Channel router with buffer insertion

Modifying timing graph to avoid given set of paths

Net delay optimization with ramptime violation removal

Process and apparatus for memory mapping

Method and BIST architecture for fast memory testing in platform-based integrated circuit

Process for designing comparators and adders of small depth

Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes

Built-in functional tester for search engines

Method for generating tech-library for logic function

Memory that allows simultaneous read requests

Sequential tester for longest prefix search engines

Sequential tester for longest prefix search engines

Memory BISR controller architecture

LSI CORP

Search engine for large-width data

Low density parity check decoder with miscorrection handling

Irregular low density parity check decoder with low syndrome error handling

Systems and methods for penalty based multi-variant encoding

Memory timing model with back-annotating

Memory mapping for parallel turbo decoding

High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks

Multimode block cipher architectures

Built in test controller with a downloadable testing program

Command language for memory testing

Memory BISR architecture for a slice

Flexible hardware architecture for ECC/HECC based cryptography

Systems and methods for reduced constraint code data processing

RRAM communication system

Generation of test sequences during memory built-in self testing of multiple memories

BOLOTOV ANATOLI A

Dynamically controlling the number of local iterations in an iterative decoder

Unified architecture for crypto functional units

Architecture and implementation method of programmable arithmetic controller for cryptographic applications

GRINCHUK MIKHAIL I

Data shredding RAID mode

High throughput frame check sequence module architecture

YANG SHAOHUA

Systems and methods for locating and correcting decoder mis-corrections

INTEL CORP

High speed flexible packet classification using network processors

ZHANG FAN

LDPC decoder trapping set identification

HAN YANG

Correcting errors in miscorrected codewords using list decoding

ANDREEV ALEXANDER E

Memory mapping for parallel turbo decoding

SEAGATE TECHNOLOGY LLC

Decoding based on randomized hard decisions

GASHKOV SERGEY B

Low depth combinational finite field multiplier