Inventor

STILES DAVID R

US28 patents

⚠️ This page may combine multiple inventors who share the name “STILES DAVID R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STILES DAVID R

ADVANCED MICRO DEVICES INC

Method and apparatus for debugging an integrated circuit

Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Method and apparatus for executing string instructions

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Branch prediction device with two levels of branch prediction cache

Branch prediction device with two levels of branch prediction cache

Method and apparatus for concurrent access to multiple physical caches

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

Multiple level cache control system with address and data pipelines

Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence

Apparatus for superscalar instruction pre-decoding using cached instruction lengths

NEXGEN MICROSYSTEMS

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

Two-level branch prediction cache

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Two-level branch prediction cache

Integrated single structure branch prediction cache

NEXGEN INC

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Two-level branch prediction cache

Apparatus for superscalar instruction predecoding using cached instruction lengths

Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

REDBACK NETWORKS INC

Alignment of TDM-based signals for packet transmission using framed and unframed operations

Ring network element and the ring network architectures it enables

Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous payload envelopes in synchronous optical networks

AMD INC

Set-associative cache memory utilizing a single bank of physical memory

STILES DAVID R

Ring network element and the ring network architectures it enables