Inventor
SRINIVAS VAISHNAV
US36 patents
⚠️ This page may combine multiple inventors who share the name “SRINIVAS VAISHNAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
31 patentsUS7075175B2Jul 11, 2006
Systems and methods for testing packaged dies
QUALCOMM INC127 citations96
US10169262B2Jan 1, 2019
Low-power clocking for a high-speed memory interface
QUALCOMM INC13 citations84
US7605618B2Oct 20, 2009
Digital output driver and input buffer using thin-oxide field effect transistors
QUALCOMM INC11 citations84
US9881656B2Jan 30, 2018
Dynamic random access memory (DRAM) backchannel communication systems and methods
QUALCOMM INC5 citations83
US7768299B2Aug 3, 2010
Voltage tolerant floating N-well circuit
QUALCOMM INC12 citations83
US9910482B2Mar 6, 2018
Memory interface with adjustable voltage and termination and methods of use
QUALCOMM INC9 citations81
US8008944B2Aug 30, 2011
Low voltage differential signaling driver with programmable on-chip resistor termination
QUALCOMM INC13 citations81
US9088445B2Jul 21, 2015
Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
QUALCOMM INC7 citations77
US7843234B2Nov 30, 2010
Break-before-make predriver and level-shifter
QUALCOMM INC7 citations73
US11120863B2Sep 14, 2021
System and method for compensating for SDRAM signal timing drift through periodic write training
QUALCOMM INC3 citations72
US9633698B2Apr 25, 2017
Dynamic control of signaling power based on an error rate
QUALCOMM INC2 citations72
US9438208B2Sep 6, 2016
Wide-band duty cycle correction circuit
QUALCOMM INC3 citations71
US10613613B2Apr 7, 2020
Memory interface with adjustable voltage and termination and methods of use
QUALCOMM INC2 citations70
US9734878B1Aug 15, 2017
Systems and methods for individually configuring dynamic random access memories sharing a common command access bus
QUALCOMM INC5 citations70
US9312326B2Apr 12, 2016
Metal-insulator-metal capacitor structures
QUALCOMM INC4 citations69
US9041148B2May 26, 2015
Metal-insulator-metal capacitor structures
QUALCOMM INC4 citations69
US9397646B2Jul 19, 2016
Delay circuit
QUALCOMM INC3 citations68
US11493949B2Nov 8, 2022
Clocking scheme to receive data
QUALCOMM INC0 citations62
US7804334B2Sep 28, 2010
High signal level compliant input/output circuits
QUALCOMM INC6 citations61
US7772887B2Aug 10, 2010
High signal level compliant input/output circuits
QUALCOMM INC6 citations61
US9032358B2May 12, 2015
Integrated circuit floorplan for compact clock distribution
QUALCOMM INC3 citations60
US7772831B2Aug 10, 2010
Systems and methods for testing packaged dies
QUALCOMM INC3 citations60
US11662765B1May 30, 2023
System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces
QUALCOMM INC1 citations58
US10224081B2Mar 5, 2019
Dynamic random access memory (DRAM) backchannel communication systems and methods
QUALCOMM INC0 citations51
US9947377B2Apr 17, 2018
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
QUALCOMM INC0 citations51
US9767868B2Sep 19, 2017
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
QUALCOMM INC1 citations51
US9871012B2Jan 16, 2018
Method and apparatus for routing die signals using external interconnects
QUALCOMM INC1 citations49
US9734890B1Aug 15, 2017
Systems and methods for individually configuring dynamic random access memories sharing a common command access bus
QUALCOMM INC1 citations49
US7656743B2Feb 2, 2010
Clock signal generation techniques for memories that do not generate a strobe
QUALCOMM INC0 citations48
US9246716B2Jan 26, 2016
Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
QUALCOMM INC1 citations44
US8957714B2Feb 17, 2015
Measure-based delay circuit
QUALCOMM INC0 citations40