Inventor
TAKEFMAN MICHAEL L
CA19 patents
⚠️ This page may combine multiple inventors who share the name “TAKEFMAN MICHAEL L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
RAMBUS INC
10 patentsUS10580465B2Mar 3, 2020
System and method for providing a configurable timing control for a memory system
RAMBUS INC7 citations83
US10168954B2Jan 1, 2019
System and method of interfacing co-processors and input/output devices via a main memory system
RAMBUS INC1 citations72
US11789662B2Oct 17, 2023
System and method of interfacing co-processors and input/output devices via a main memory system
RAMBUS INC0 citations62
US11422749B2Aug 23, 2022
System and method of interfacing co-processors and input/output devices via a main memory system
RAMBUS INC0 citations62
US10942682B2Mar 9, 2021
System and method of interfacing co-processors and input/output devices via a main memory system
RAMBUS INC0 citations62
US11640836B2May 2, 2023
System and method for providing a configurable timing control for a memory system
RAMBUS INC0 citations61
US11062743B2Jul 13, 2021
System and method for providing a configurable timing control for a memory system
RAMBUS INC0 citations61
US11061841B2Jul 13, 2021
System and method for implementing a multi-threaded device driver in a computer system
RAMBUS INC1 citations60
US10725704B2Jul 28, 2020
System and method of interfacing co-processors and input/output devices via a main memory system
RAMBUS INC0 citations51
US10719466B2Jul 21, 2020
System and method for implementing a multi-threaded device driver in a computer system
RAMBUS INC0 citations50
DIABLO TECH INC
5 patentsUS9552175B2Jan 24, 2017
System and method for providing a command buffer in a memory system
DIABLO TECH INC17 citations83
US9444495B2Sep 13, 2016
System and method of interfacing co-processors and input/output devices via a main memory system
DIABLO TECH INC4 citations83
US9449651B2Sep 20, 2016
System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset
DIABLO TECH INC3 citations71
US9779020B2Oct 3, 2017
System and method for providing an address cache for memory map learning
DIABLO TECH INC0 citations51
US9575908B2Feb 21, 2017
System and method for unlocking additional functions of a module
DIABLO TECH INC1 citations51