Inventor

SURISETTY CHARAN VEERA VENKATA SATYA

US18 patents

⚠️ This page may combine multiple inventors who share the name “SURISETTY CHARAN VEERA VENKATA SATYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SURISETTY CHARAN VEERA VENKATA SATYA

IBM

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Low resistance replacement metal gate structure

Nanosheet isolation for bulk CMOS non-planar devices

Stable contact on one-sided gate tie-down structure

Forming dual contact silicide using metal multi-layer and ion beam mixing

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Semiconductor fabrication method using stop layer

Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Low resistance replacement metal gate structure

Semiconductor structure containing low-resistance source and drain contacts

Nanosheet isolation for bulk CMOS non-planar devices

Semiconductor structure containing low-resistance source and drain contacts

Semiconductor structure containing low-resistance source and drain contacts

Capacitance reduction for advanced technology nodes

GLOBALFOUNDRIES INC

Methods of forming replacement gate structures on semiconductor devices and the resulting device

Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween

Methods for replacing gate sidewall materials with a low-k spacer

Integrated circuits having gate cap protection and methods of forming the same