P

Inventor

COHEN STEPHAN A

US18 patents
⚠️ This page may combine multiple inventors who share the name “COHEN STEPHAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

16 patents
US5530293AJun 25, 1996

Carbon-free hydrogen silsesquioxane with dielectric constant less than 3.2 annealed in hydrogen for integrated circuits

IBM75 citations96
US7223670B2May 29, 2007

DUV laser annealing and stabilization of SiCOH films

IBM33 citations92
US6452276B1Sep 17, 2002

Ultra thin, single phase, diffusion barrier for metal conductors

IBM38 citations91
US10224242B1Mar 5, 2019

Low-resistivity metallic interconnect structures

IBM15 citations86
US8962479B2Feb 24, 2015

Interconnect structures containing nitrided metallic residues

IBM6 citations84
US7256146B2Aug 14, 2007

Method of forming a ceramic diffusion barrier layer

IBM5 citations74
US6940173B2Sep 6, 2005

Interconnect structures incorporating low-k dielectric barrier films

IBM6 citations74
US9698043B1Jul 4, 2017

Shallow trench isolation for semiconductor devices

IBM5 citations73
US9281211B2Mar 8, 2016

Nanoscale interconnect structure

IBM5 citations73
US6726996B2Apr 27, 2004

Laminated diffusion barrier

IBM8 citations69
US8362596B2Jan 29, 2013

Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same

IBM4 citations63
US7252875B2Aug 7, 2007

Diffusion barrier with low dielectric constant and semiconductor device containing same

IBM2 citations63
US9613900B2Apr 4, 2017

Nanoscale interconnect structure

IBM1 citations52
US9006895B2Apr 14, 2015

Interconnect structures containing nitrided metallic residues

IBM1 citations52
US10204823B2Feb 12, 2019

Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing

IBM0 citations51
US9922866B2Mar 20, 2018

Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing

IBM0 citations51

BALSEANU MIHAELA

2 patents