Inventor
CHOI YOUNSUNG
US16 patents
⚠️ This page may combine multiple inventors who share the name “CHOI YOUNSUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TEXAS INSTRUMENTS INC
12 patentsUS9812452B2Nov 7, 2017
Method to form silicide and contact at embedded epitaxial facet
TEXAS INSTRUMENTS INC4 citations72
US10026837B2Jul 17, 2018
Embedded SiGe process for multi-threshold PMOS transistors
TEXAS INSTRUMENTS INC2 citations71
US9735159B2Aug 15, 2017
Optimized layout for relaxed and strained liner in single stress liner technology
TEXAS INSTRUMENTS INC2 citations71
US11251093B2Feb 15, 2022
Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
TEXAS INSTRUMENTS INC0 citations59
US10008499B2Jun 26, 2018
Method to form silicide and contact at embedded epitaxial facet
TEXAS INSTRUMENTS INC0 citations51
US9508601B2Nov 29, 2016
Method to form silicide and contact at embedded epitaxial facet
TEXAS INSTRUMENTS INC0 citations51
US9947765B2Apr 17, 2018
Dummy gate placement methodology to enhance integrated circuit performance
TEXAS INSTRUMENTS INC0 citations50
US9496142B2Nov 15, 2016
Dummy gate placement methodology to enhance integrated circuit performance
TEXAS INSTRUMENTS INC0 citations50
US10734290B2Aug 4, 2020
Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
TEXAS INSTRUMENTS INC0 citations49
US10134643B2Nov 20, 2018
Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
TEXAS INSTRUMENTS INC0 citations49
US9583488B2Feb 28, 2017
Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
TEXAS INSTRUMENTS INC0 citations49
US10559469B2Feb 11, 2020
Dual pocket approach in PFETs with embedded SI-GE source/drain
TEXAS INSTRUMENTS INC0 citations40