Inventor

LEVI AMITAY

US63 patents

⚠️ This page may combine multiple inventors who share the name “LEVI AMITAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEVI AMITAY

SPIN MEMORY INC

Three dimensional perpendicular magnetic junction with thin-film transistor

Shared bit line array architecture for magnetoresistive memory

Integration of epitaxially grown channel selector with two terminal resistive switching memory element

Integration of epitaxially grown channel selector with MRAM device

Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels

Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor

Dual gate memory devices

Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels

Annular vertical Si etched channel MOS devices

Fabrication methods of forming annular vertical SI etched channel MOS devices

Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymers

Adjustable current selectors

Perpendicular magnetic tunnel junction memory cells having shared source contacts

Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)

Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)

Dual channel/gate vertical field-effect transistor (FET) for use with a perpendicular magnetic tunnel junction (PMTJ)

Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices

SILICON STORAGE TECH INC

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Semiconductor memory array of floating gate memory cells with program/erase and select gates

Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system

Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling

Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling

Semiconductor array of floating gate memory cells and strap regions

Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates

Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing

Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric

High endurance non-volatile memory cell and array

Non-volatile memory cell with buried select gate, and method of making same

Method of forming a semiconductor array of floating gate memory cells and strap regions

Semiconductor memory array of floating gate memory cells with program/erase and select gates

Method of planarizing a semiconductor die

Method of planarizing a semiconductor die

INTEGRATED SILICON SOLUTION CAYMAN INC

Three dimensional perpendicular magnetic tunnel junction with thin film transistor array

Three dimensional perpendicular magnetic tunnel junction with thin film transistor array

Compact and efficient CMOS inverter

DRAM with selective epitaxial cell transistor

High density 3D magnetic random access memory (MRAM) cell integration using wafer cut and transfer

DRAM with selective epitaxial transistor and buried bitline

DRAM with selective epitaxial cell transistor

Compact and efficient CMOS inverter

SPIN TRANSFER TECH

Methods of fabricating dual threshold voltage devices

Methods of fabricating contacts for cylindrical devices

Dual threshold voltage devices with stacked gates

Methods of fabricating dual threshold voltage devices with stacked gates

SPIN TRANSFER TECH INC

Predicting tunnel barrier endurance using redundant memory structures

Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)

DO NHAN

Non-volatile memory cell with self aligned floating and erase gates, and method of making same

LEVI AMITAY

Magnetic random access memory cells having improved size and shape characteristics

KOTOV ALEXANDER

Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby