Inventor

CASTRO HERNAN A

US118 patents

⚠️ This page may combine multiple inventors who share the name “CASTRO HERNAN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CASTRO HERNAN A

MICRON TECHNOLOGY INC

Accessing memory cells in parallel in a cross-point array

Interconnection for memory electrodes

Apparatuses and methods for bi-directional access of crosspoint arrays

Memory array decoding and interconnects

Operations on memory cells

Comparing input data to stored data

Compensation for threshold voltage variation of memory cell components

Metallization scheme for integrated circuit

Connections for memory electrode lines

Apparatuses and methods for bi-directional access of cross-point arrays

Interconnection for memory electrodes

Metallization scheme for integrated circuit

Connections for memory electrode lines

Memory device architecture

Three-state programming of memory cells

Techniques for programming a memory cell

Accessing memory cells in parallel in a cross-point array

Apparatuses and methods for bi-directional access of cross-point arrays

Operational signals generated from capacitive stored charge

Interconnection for memory electrodes

Interconnection for memory electrodes

Interconnection for memory electrodes

Multi-state programming of memory cells

Methods and apparatuses for modulating threshold voltages of memory cells

Memory tile access and selection patterns

Pulse based multi-level cell programming

INTEL CORP

Four quadrant synapse cell employing single column summing line

Synapse cell employing dual gate transistor structure

Semiconductor cell for neural network employing a four-quadrant multiplier

Neural network accomodating parallel synaptic weight adjustments for correlation learning algorithms

Redundancy decoding circuit using n-channel transistors

Radiation shield for EPROM cells

Voltage threshold measuring circuit

Reset circuit for redundant memory using CAM cells

EXCLUSIVE-OR cell for neural network and the like

Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network

Reset refresh techniques for self-selecting memory

Path isolation in a memory device

Path isolation in a memory device

Path isolation in a memory device

Memory controller for reducing capacitive coupling in a cross-point memory

Neural network accommodating parallel synaptic weight adjustments in a single cycle

Charge domain differential conductance synapse cell for neural networks

Neural network employing absolute value calculating synapse

Charge domain synapse cell

Multi-quadrant charge domain synapse cell

Neural network exhibiting improved tolerance to temperature and power supply variations

CASTRO HERNAN A

Path isolation in a memory device

Method and apparatus for combined electrochemical synthesis and detection of analytes

PELLIZZER FABIO

Etch bias homogenization