Inventor

HOVIS WILLIAM PAUL

US64 patents

⚠️ This page may combine multiple inventors who share the name “HOVIS WILLIAM PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOVIS WILLIAM PAUL

IBM

Bulk FinFET device

Polysilicon conductor width measurement for 3-dimensional FETs

Memory device having programmable device width, method of programming, and method of setting device width for memory device

Electrical open/short contact alignment structure for active region vs. gate region

Compression architecture for system memory application

Multiple memory bank command for synchronous DRAMs

Address wrap function for addressable memory devices

Bulk FinFET device

Bulk FinFET device

Method and stacked memory structure for implementing enhanced cooling of memory devices

FinFET body contact structure

Method and apparatus to reduce bias temperature instability (BTI) effects

Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock

Method and apparatus for detecting array degradation and logic degradation

Method and apparatus for protecting eFuse information

Method and testing circuit for tracking transistor stress degradation

eFuse sense circuit

Memory controller and method for optimized read/modify/write performance

Memory controller and method for handling DMA operations during a page copy

Memory controller and method for optimized read/modify/write performance

Implementing memory read data eye stretcher

Method and apparatus for improving performance margin in logic paths

Monitoring of solid state memory devices in active memory system utilizing redundant devices

Handling DMA operations during a page copy

Diagnostic interface architecture for memory device

Method and system for improving DRAM subsystem performance using burst refresh control

Memory device verification of multiple write operations

Method, apparatus, and computer program product for implementing enhanced DRAM interface checking

Handling DMA requests in a virtual memory environment

Implementing redundant memory access using multiple controllers on the same bank of memory

Implementing directory organization to selectively optimize performance or reliability

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Method and apparatus for controlling AC power during scan operations in scannable latches

Diagnostic interface architecture for memory device

FinFET body contact structure

Implementing memory read data eye stretcher

Memory controller and method for optimized read/modify/write performance

Semiconductor scheme for reduced circuit area in a simplified process

Encoding of message onto strobe signals

MICROSOFT TECHNOLOGY LICENSING LLC

Thermal arrangement of modules in server assemblies

Voltage based thermal control of processing device

Through-board power control arrangements for integrated circuit devices

Clock frequency adjustment for workload changes in integrated circuit devices

Integrated circuit power domains segregated among power supply phases

Load adjusted populations of integrated circuit decoupling capacitors

Load adjusted populations of integrated circuit decoupling capacitors

Predictive voltage transient reduction in integrated circuits

Thermal rotation of power supply phases

BARTLEY GERALD KEITH

Digital data architecture employing redundant links in a daisy chain of component modules