Inventor
MOONDANOS JOHN
US4 patents
Patents
4 patentsUS6792581B2Sep 14, 2004
Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification
INTEL CORP9 citations69
US6564358B2May 13, 2003
Method and system for formal verification of a circuit model using binary decision diagrams
INTEL CORP12 citations65
US7117465B2Oct 3, 2006
Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs
INTEL CORP4 citations59
US7159201B2Jan 2, 2007
Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification
INTEL CORP4 citations58