Inventor

KAPOOR SHAKTI

US84 patents

⚠️ This page may combine multiple inventors who share the name “KAPOOR SHAKTI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAPOOR SHAKTI

IBM

Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems

Identifying stale entries in address translation cache

System and method for using resource pools and instruction pools for processor design verification and validation

System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

Method, system and computer program product to stress and test logical partition isolation features

System and method for re-shuffling test case instruction orders for processor design verification and validation

Replicating test case data into a cache with non-naturally aligned data boundaries

Efficient testing of direct memory address translation

Efficient testing of direct memory address translation

System and method for testing SLB and TLB cells during processor design verification and validation

System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation

System and method for verification of cache snoop logic and coherency between instruction &amp; data caches for processor design verification and validation

System and method for testing a large memory area during processor design verification and validation

Replicating test code and test data into a cache with non-naturally aligned data boundaries

Synchronization of hardware agents in a computer system

Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment

System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation

System and method for pseudo-random test pattern memory allocation for processor design verification and validation

Testing a non-core MMU

System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation

Method and system for low level testing of central electronics complex hardware using Test nano Kernel

Method, system, and apparatus for reducing processor latency

Transactional memory performance and footprint

Transactional memory performance and footprint

Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries

Hazard generating for speculative cores in a microprocessor

Validation of store coherence relative to page translation invalidation

Validation of store coherence relative to page translation invalidation

List insertion in test segments with non-naturally aligned data boundaries

Method, system, and apparatus for stress testing memory translation tables

Method, system, and apparatus for stress testing memory translation tables

Identifying stale entries in address translation cache

Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systems

Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics

Method and system for testing remote I/O functionality

Processor performance monitor that logs reasons for reservation loss

System and method for testing multiple processor modes for processor design verification and validation

I/O stress test

Efficiently generating effective address translations for memory management test cases

Stress testing a processor memory with a link stack

Embedded page size hint for page fault resolution

Replicating test case data into a cache with non-naturally aligned data boundaries

Method, system, and apparatus for reducing processor latency

Transactional memory operation success rate

Transactional memory operation success rate

DUSANAPUDI MANOJ

Hardware verification using acceleration platform

CHOUDHURY SHUBHODEEP ROY

System and method for generating fast instruction and data interrupts for processor design verification and validation

GLOBALFOUNDRIES INC

Efficient validation of coherency between processor cores and accelerators in computer systems

ALAPATI SANGRAM

Method and system for stealing interrupt vectors

ARORA SAMPAN

Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode

System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation