Inventor

ONO TOSHINOBU

JP3 patents

⚠️ This page may combine multiple inventors who share the name “ONO TOSHINOBU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEC CORP

1 patent

US6334199B1Dec 25, 2001

Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method

NEC CORP22 citations87

NEC USA INC

1 patent

US5502730AMar 26, 1996

Partial scan testability utilizing reconvergence through sequential elements

NEC USA INC9 citations69

NOGUCHI KOICHIRO

1 patent

US8441277B2May 14, 2013

Semiconductor testing device, semiconductor device, and testing method

NOGUCHI KOICHIRO0 citations36