Inventor

KUMAR RAGHAVAN

US63 patents

⚠️ This page may combine multiple inventors who share the name “KUMAR RAGHAVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUMAR RAGHAVAN

INTEL CORP

Binary, ternary and bit serial compute-in-memory circuits

Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations

Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

Compute in memory circuits with time-to-digital computation

Binary, ternary and bit serial compute-in-memory circuits

In-memory multiply and accumulate with global charge-sharing

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Techniques for current-sensing circuit design for compute-in-memory

Digital bit-serial multi-multiply-and-accumulate compute in memory

Event driven and time hopping neural network

Compute near memory convolution accelerator

In-memory analog neural cache

Unified accelerator for classical and post-quantum digital signature schemes in computing environments

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Accelerators for post-quantum cryptography secure hash-based signing and verification

Programmable interface to in-memory cache processor

Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions

Device, system, and method to change a consistency of behavior by a cell circuit

Neural network with reconfigurable sparse connectivity and online learning

Memory device with multiple memory arrays to facilitate in-memory computation

Linear masking circuits for side-channel immunization of advanced encryption standard hardware

Neuromorphic circuits for storing and generating connectivity information

LSTM circuit with selective input computation

Technologies for memory and I/O efficient operations on homomorphically encrypted data

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

LSTM circuit with selective input computation

Accelerators for post-quantum cryptography secure hash-based signing and verification

Secure PUF-based device authentication using adversarial challenge selection

Odd index precomputation for authentication path computation

FinFET transistor based resistive random access memory

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Reconfigurable memory compression techniques for deep neural networks

Deep in memory architecture using resistive switches

Secure PUF-based device authentication using adversarial challenge selection

Low synch dedicated accelerator with in-memory computation capability

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Odd index precomputation for authentication path computation

Post quantum public key signature operation for reconfigurable circuit devices

Oscillator circuitry to facilitate in-memory computation

Power side-channel attack resistant advanced encryption standard accelerator processor

Pipeline circuit architecture to provide in-memory computation functionality

Self-calibrated von-neumann extractor

Programmable interface to in-memory cache processor

Mixed-coordinate point multiplication

Reconfigurable neuro-synaptic cores for spiking neural network

Sumbul Huseyin Ekin

Full-rail digital read compute-in-memory circuit