Inventor

CHEN GREGORY K

US46 patents

⚠️ This page may combine multiple inventors who share the name “CHEN GREGORY K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN GREGORY K

INTEL CORP

Binary, ternary and bit serial compute-in-memory circuits

Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations

Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

Compute in memory circuits with time-to-digital computation

Binary, ternary and bit serial compute-in-memory circuits

In-memory multiply and accumulate with global charge-sharing

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Techniques for current-sensing circuit design for compute-in-memory

Digital bit-serial multi-multiply-and-accumulate compute in memory

Spatially divided circuit-switched channels for a network-on-chip

Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)

Event driven and time hopping neural network

Combined guaranteed throughput and best effort network-on-chip

Compute near memory convolution accelerator

Multi-chip module having a stacked logic chip and memory stack

Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions

Neural network with reconfigurable sparse connectivity and online learning

Parallel direction decode circuits for network-on-chip

Link delay based routing apparatus for a network-on-chip

Neuromorphic circuits for storing and generating connectivity information

End-to-end data protection for compute in memory (CIM)/compute near memory (CNM)

LSTM circuit with selective input computation

High bandwidth core to network-on-chip interface

Compute near memory with backend memory

LSTM circuit with selective input computation

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Reconfigurable memory compression techniques for deep neural networks

High bandwidth core to network-on-chip interface

Compute near memory with backend memory

Interconnection scheme for reconfigurable neuromorphic hardware

Reconfigurable neuro-synaptic cores for spiking neural network

Scalable free-running neuromorphic computer

Processor array for processing sparse binary neural networks

Neuromorphic circuits for storing and generating connectivity information

Programmable neuron core with on-chip learning and stochastic time step control

Pipelined hybrid packet/circuit-switched network-on-chip

Pointer chasing across distributed memory

System for multicast and reduction communications on a network-on-chip

Edge-aware synchronization of a data signal

Scalable crossbar apparatus and method for arranging crossbar circuits

Adaptively switched network-on-chip

KOSONOCKY STEPHEN V

Power supply monitor

Sumbul Huseyin Ekin

Full-rail digital read compute-in-memory circuit

ANDERS MARK A

Architecture and method for hybrid circuit-switched and packet-switched router

CHEN GREGORY K

Apparatus and method for a digital neuromorphic processor