Inventor

KNAG PHIL

US38 patents

⚠️ This page may combine multiple inventors who share the name “KNAG PHIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KNAG PHIL

INTEL CORP

Binary, ternary and bit serial compute-in-memory circuits

Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations

Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

Compute in memory circuits with time-to-digital computation

Binary, ternary and bit serial compute-in-memory circuits

In-memory multiply and accumulate with global charge-sharing

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Techniques for current-sensing circuit design for compute-in-memory

Digital bit-serial multi-multiply-and-accumulate compute in memory

Event driven and time hopping neural network

Compute near memory convolution accelerator

Multi-chip module having a stacked logic chip and memory stack

In-memory analog neural cache

Programmable interface to in-memory cache processor

Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions

Neural network with reconfigurable sparse connectivity and online learning

Memory device with multiple memory arrays to facilitate in-memory computation

LSTM circuit with selective input computation

Compute near memory with backend memory

LSTM circuit with selective input computation

FinFET transistor based resistive random access memory

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Reconfigurable memory compression techniques for deep neural networks

Deep in memory architecture using resistive switches

Low synch dedicated accelerator with in-memory computation capability

Compute near memory with backend memory

Oscillator circuitry to facilitate in-memory computation

Pipeline circuit architecture to provide in-memory computation functionality

Programmable interface to in-memory cache processor

Reconfigurable neuro-synaptic cores for spiking neural network

Scalable free-running neuromorphic computer

Memoryless weight storage hardware for neural networks

Processor array for processing sparse binary neural networks

Weight prefetch for in-memory neural network execution

Programmable neuron core with on-chip learning and stochastic time step control

Sumbul Huseyin Ekin

Full-rail digital read compute-in-memory circuit

UNIV MICHIGAN REGENTS

Sparse neuromorphic processor