P

Inventor

CHEN JEI MING

TW36 patents
⚠️ This page may combine multiple inventors who share the name “CHEN JEI MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAIWAN SEMICONDUCTOR MFG CO LTD

16 patents
US10332746B1Jun 25, 2019

Post UV cure for gapfill improvement

TAIWAN SEMICONDUCTOR MFG CO LTD9 citations83
US11887851B2Jan 30, 2024

Method for forming and using mask

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations75
US11482411B2Oct 25, 2022

Semiconductor device and method

TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US11842922B2Dec 12, 2023

Method for forming interconnect structure

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US10777466B2Sep 15, 2020

Semiconductor Fin cutting process and structures formed thereby

TAIWAN SEMICONDUCTOR MFG CO LTD4 citations71
US10957585B2Mar 23, 2021

Semiconductor device and method of forming the same

TAIWAN SEMICONDUCTOR MFG CO LTD5 citations65
US12341011B2Jun 24, 2025

Method for forming and using mask

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12322590B2Jun 3, 2025

Semiconductor device and method

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12308283B2May 20, 2025

Method for forming interconnect structure

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12087644B2Sep 10, 2024

Methods of determining process recipes and forming a semiconductor device

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11854798B2Dec 26, 2023

Semiconductor device and method

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10727064B2Jul 28, 2020

Post UV cure for gapfill improvement

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61
US11990375B2May 21, 2024

Semiconductor Fin cutting process and structures formed thereby

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations60
US11380593B2Jul 5, 2022

Semiconductor fin cutting process and structures formed thereby

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations60
US11101366B2Aug 24, 2021

Remote plasma oxide layer

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations53
US12217971B2Feb 4, 2025

Method for forming semiconductor device

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52

UNITED MICROELECTRONICS CORP

14 patents
US8709901B1Apr 29, 2014

Method of forming an isolation structure

UNITED MICROELECTRONICS CORP26 citations92
US7378343B2May 27, 2008

Dual damascence process utilizing teos-based silicon oxide cap layer having reduced carbon content

UNITED MICROELECTRONICS CORP20 citations91
US8951884B1Feb 10, 2015

Method for forming a FinFET structure

UNITED MICROELECTRONICS CORP7 citations83
US8937369B2Jan 20, 2015

Transistor with non-uniform stress layer with stress concentrated regions

UNITED MICROELECTRONICS CORP7 citations83
US9362358B2Jun 7, 2016

Spatial semiconductor structure

UNITED MICROELECTRONICS CORP6 citations81
US9502305B2Nov 22, 2016

Method for manufacturing CMOS transistor

UNITED MICROELECTRONICS CORP4 citations73
US8927388B2Jan 6, 2015

Method of fabricating dielectric layer and shallow trench isolation

UNITED MICROELECTRONICS CORP4 citations72
US9034759B2May 19, 2015

Method for forming interlevel dielectric (ILD) layer

UNITED MICROELECTRONICS CORP2 citations62
US6960522B2Nov 1, 2005

Method for making damascene interconnect with bilayer capping film

UNITED MICROELECTRONICS CORP4 citations61
US7514347B2Apr 7, 2009

Interconnect structure and fabricating method thereof

UNITED MICROELECTRONICS CORP2 citations59
US7439154B2Oct 21, 2008

Method of fabricating interconnect structure

UNITED MICROELECTRONICS CORP6 citations59
US9343573B2May 17, 2016

Method of fabrication transistor with non-uniform stress layer with stress concentrated regions

UNITED MICROELECTRONICS CORP0 citations51
US9034726B2May 19, 2015

Semiconductor process

UNITED MICROELECTRONICS CORP1 citations51
US9105582B2Aug 11, 2015

Spatial semiconductor structure and method of fabricating the same

UNITED MICROELECTRONICS CORP0 citations49

UNITED MICROELECTRTONICS CORP

1 patent

LIU CHIH-CHIEN

1 patent

CHIEN CHIN-CHENG

1 patent

LU TSUO-WEN

1 patent

Wang shao-wei

1 patent

CHEN JEI-MING

1 patent