Inventor
TIWARI SANDIP
US47 patents
⚠️ This page may combine multiple inventors who share the name “TIWARI SANDIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
30 patentsUS6333532B1Dec 25, 2001
Patterned SOI regions in semiconductor chips
IBM232 citations99
US6057212AMay 2, 2000
Method for making bonded metal back-plane substrates
IBM388 citations98
US5998292ADec 7, 1999
Method for making three dimensional circuit integration
IBM669 citations98
US5508543AApr 16, 1996
Low voltage memory
IBM140 citations98
US5937295AAug 10, 1999
Nano-structure memory device
IBM163 citations97
US5714766AFeb 3, 1998
Nano-structure memory device
IBM372 citations97
US6750471B2Jun 15, 2004
Molecular memory & logic
IBM99 citations96
US6248626B1Jun 19, 2001
Floating back gate electrically erasable programmable read-only memory (EEPROM)
IBM72 citations96
US6236060B1May 22, 2001
Light emitting structures in back-end of line silicon technology
IBM65 citations96
US6137128AOct 24, 2000
Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
IBM67 citations96
US6177289B1Jan 23, 2001
Lateral trench optical detectors
IBM71 citations95
US5757038AMay 26, 1998
Self-aligned dual gate MOSFET with an ultranarrow channel
IBM48 citations95
US6472705B1Oct 29, 2002
Molecular memory & logic
IBM58 citations94
US6445032B1Sep 3, 2002
Floating back gate electrically erasable programmable read-only memory(EEPROM)
IBM24 citations93
US6069819AMay 30, 2000
Variable threshold voltage DRAM cell
IBM22 citations93
US4558509ADec 17, 1985
Method for fabricating a gallium arsenide semiconductor device
IBM38 citations93
US6800518B2Oct 5, 2004
Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering
IBM44 citations92
US6756257B2Jun 29, 2004
Patterned SOI regions on semiconductor chips
IBM34 citations92
US5098859AMar 24, 1992
Method for forming distributed barrier compound semiconductor contacts
IBM36 citations92
US5086321AFeb 4, 1992
Unpinned oxide-compound semiconductor structures and method of forming same
IBM28 citations92
US5920086AJul 6, 1999
Light emitting device
IBM20 citations90
US6350321B1Feb 26, 2002
UHV horizontal hot wall cluster CVD/growth design
IBM28 citations88
US4593307AJun 3, 1986
High temperature stable ohmic contact to gallium arsenide
IBM22 citations82
US6101117AAug 8, 2000
Two transistor single capacitor ferroelectric memory
IBM10 citations74
US4987095AJan 22, 1991
Method of making unpinned oxide-compound semiconductor structures
IBM7 citations74
US4849802AJul 18, 1989
Thermally stable low resistance contact
IBM11 citations74
US4586071AApr 29, 1986
Heterostructure bipolar transistor
IBM17 citations74
US5162891ANov 10, 1992
Group III-V heterostructure devices having self-aligned graded contact diffusion regions and method for fabricating same
IBM8 citations73
US5158896AOct 27, 1992
Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions
IBM11 citations73
US6281551B1Aug 28, 2001
Back-plane for semiconductor device
IBM6 citations72
CORNELL RES FOUNDATION INC
5 patentsUS6600173B2Jul 29, 2003
Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
CORNELL RES FOUNDATION INC436 citations99
US6953958B2Oct 11, 2005
Electronic gain cell based charge sensor
CORNELL RES FOUNDATION INC222 citations98
US7057234B2Jun 6, 2006
Scalable nano-transistor and memory using back-side trapping
CORNELL RES FOUNDATION INC35 citations93
US7365398B2Apr 29, 2008
Compact SRAMs and other multiple transistor structures
CORNELL RES FOUNDATION INC16 citations84
US6534819B2Mar 18, 2003
Dense backplane cell for configurable logic
CORNELL RES FOUNDATION INC16 citations84