Inventor

LILAK AARON

US47 patents

Patents

47 patents

US11264512B2Mar 1, 2022

Thin film transistors having U-shaped features

INTEL CORP6 citations86

US11367722B2Jun 21, 2022

Stacked nanowire transistor structure with different channel geometries for stress

INTEL CORP6 citations74

US11764263B2Sep 19, 2023

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

INTEL CORP2 citations73

US11411119B2Aug 9, 2022

Double gated thin film transistors

INTEL CORP3 citations73

US11387238B2Jul 12, 2022

Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

INTEL CORP2 citations73

US11362189B2Jun 14, 2022

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

INTEL CORP0 citations63

US11721735B2Aug 8, 2023

Thin film transistors having U-shaped features

INTEL CORP0 citations63

US11664373B2May 30, 2023

Isolation walls for vertically stacked transistor structures

INTEL CORP1 citations63

US11437405B2Sep 6, 2022

Transistors stacked on front-end p-type transistors

INTEL CORP1 citations63

US11239232B2Feb 1, 2022

Isolation walls for vertically stacked transistor structures

INTEL CORP1 citations63

US12328864B2Jun 10, 2025

3D 1T1C stacked dram structure and method to fabricate

INTEL CORP0 citations62

US12288807B2Apr 29, 2025

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

INTEL CORP0 citations62

US12255137B2Mar 18, 2025

Sideways vias in isolation areas to contact interior layers in stacked devices

INTEL CORP0 citations62

US12224202B2Feb 11, 2025

Forming an oxide volume within a fin

INTEL CORP0 citations62

US12148806B2Nov 19, 2024

Stacked source-drain-gate connection and process for forming such

INTEL CORP0 citations62

US12100623B2Sep 24, 2024

Vertically stacked finFETs and shared gate patterning

INTEL CORP0 citations62

US11942416B2Mar 26, 2024

Sideways vias in isolation areas to contact interior layers in stacked devices

INTEL CORP0 citations62

US11916118B2Feb 27, 2024

Stacked source-drain-gate connection and process for forming such

INTEL CORP0 citations62

US11894372B2Feb 6, 2024

Stacked trigate transistors with dielectric isolation and process for forming such

INTEL CORP0 citations62

US11849572B2Dec 19, 2023

3D 1T1C stacked DRAM structure and method to fabricate

INTEL CORP0 citations62

US11830933B2Nov 28, 2023

Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

INTEL CORP0 citations62

US11798838B2Oct 24, 2023

Capacitance reduction for semiconductor devices based on wafer bonding

INTEL CORP0 citations62

US11798991B2Oct 24, 2023

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

INTEL CORP0 citations62

US11769814B2Sep 26, 2023

Device including air gapping of gate spacers and other dielectrics and process for providing such

INTEL CORP0 citations62

US11764104B2Sep 19, 2023

Forming an oxide volume within a fin

INTEL CORP0 citations62

US11646352B2May 9, 2023

Stacked source-drain-gate connection and process for forming such

INTEL CORP0 citations62

US11594533B2Feb 28, 2023

Stacked trigate transistors with dielectric isolation between first and second semiconductor fins

INTEL CORP0 citations62

US11532719B2Dec 20, 2022

Transistors on heterogeneous bonding layers

INTEL CORP0 citations62

US11482621B2Oct 25, 2022

Vertically stacked CMOS with upfront M0 interconnect

INTEL CORP0 citations62

US11462568B2Oct 4, 2022

Stacked thin film transistors

INTEL CORP0 citations62

US10861870B2Dec 8, 2020

Inverted staircase contact for density improvement to 3D stacked devices

INTEL CORP1 citations62

US11527613B2Dec 13, 2022

Removal of a bottom-most nanowire from a nanowire device stack

INTEL CORP0 citations61

US10892326B2Jan 12, 2021

Removal of a bottom-most nanowire from a nanowire device stack

INTEL CORP0 citations61

US11515318B2Nov 29, 2022

3D floating-gate multiple-input device

INTEL CORP1 citations59

US11495683B2Nov 8, 2022

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

INTEL CORP0 citations59

US12020929B2Jun 25, 2024

Epitaxial layer with substantially parallel sides

INTEL CORP0 citations52

US11776898B2Oct 3, 2023

Sidewall interconnect metallization structures for integrated circuit devices

INTEL CORP0 citations52

US11605565B2Mar 14, 2023

Three dimensional integrated circuits with stacked transistors

INTEL CORP0 citations52

US11574910B2Feb 7, 2023

Device with air-gaps to reduce coupling capacitance and process for forming such

INTEL CORP0 citations52

US11380684B2Jul 5, 2022

Stacked transistor architecture including nanowire or nanoribbon thin film transistors

INTEL CORP0 citations52

US11049861B2Jun 29, 2021

Method, device and system to provide capacitance for a dynamic random access memory cell

INTEL CORP0 citations52

US12513984B2Dec 30, 2025

Double-sided integrated circuit transistor structures with depopulated bottom channel regions

INTEL CORP0 citations51

US11569238B2Jan 31, 2023

Vertical memory cells

INTEL CORP0 citations50

LILAK AARON

Patents

Thin film transistors having U-shaped features

Stacked nanowire transistor structure with different channel geometries for stress

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Double gated thin film transistors

Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

Stacked self-aligned transistors with single workfunction metal

Stacked transistor structures with asymmetrical terminal interconnects

Vertically stacked finFETs and shared gate patterning

Stress compensation for wafer to wafer bonding

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Thin film transistors having U-shaped features

Isolation walls for vertically stacked transistor structures

Transistors stacked on front-end p-type transistors

Isolation walls for vertically stacked transistor structures

3D 1T1C stacked dram structure and method to fabricate

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

Sideways vias in isolation areas to contact interior layers in stacked devices

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Vertically stacked finFETs and shared gate patterning

Sideways vias in isolation areas to contact interior layers in stacked devices

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process for forming such

3D 1T1C stacked DRAM structure and method to fabricate

Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach

Capacitance reduction for semiconductor devices based on wafer bonding

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

Device including air gapping of gate spacers and other dielectrics and process for providing such

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation between first and second semiconductor fins

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Stacked thin film transistors

Inverted staircase contact for density improvement to 3D stacked devices

Removal of a bottom-most nanowire from a nanowire device stack

Removal of a bottom-most nanowire from a nanowire device stack

3D floating-gate multiple-input device

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Epitaxial layer with substantially parallel sides

Sidewall interconnect metallization structures for integrated circuit devices

Three dimensional integrated circuits with stacked transistors

Device with air-gaps to reduce coupling capacitance and process for forming such

Stacked transistor architecture including nanowire or nanoribbon thin film transistors

Method, device and system to provide capacitance for a dynamic random access memory cell

Double-sided integrated circuit transistor structures with depopulated bottom channel regions

Vertical memory cells