P

Inventor

CEA STEPHEN

US19 patents

Patents

19 patents
US7045408B2May 16, 2006

Integrated circuit with improved channel stress properties and a method for making it

INTEL CORP32 citations92
US11527612B2Dec 13, 2022

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

INTEL CORP6 citations74
US11367722B2Jun 21, 2022

Stacked nanowire transistor structure with different channel geometries for stress

INTEL CORP6 citations74
US11824107B2Nov 21, 2023

Wrap-around contact structures for semiconductor nanowires and nanoribbons

INTEL CORP2 citations73
US11527640B2Dec 13, 2022

Wrap-around contact structures for semiconductor nanowires and nanoribbons

INTEL CORP3 citations73
US11276780B2Mar 15, 2022

Transistor contact area enhancement

INTEL CORP2 citations73
US12176429B2Dec 24, 2024

Wrap-around contact structures for semiconductor nanowires and nanoribbons

INTEL CORP0 citations62
US11984449B2May 14, 2024

Channel structures with sub-fin dopant diffusion blocking layers

INTEL CORP0 citations62
US11843052B2Dec 12, 2023

Transistor contact area enhancement

INTEL CORP0 citations62
US11521968B2Dec 6, 2022

Channel structures with sub-fin dopant diffusion blocking layers

INTEL CORP0 citations62
US12336278B2Jun 17, 2025

Gate-all-around integrated circuit structures having high mobility

INTEL CORP0 citations61
US11538806B2Dec 27, 2022

Gate-all-around integrated circuit structures having high mobility

INTEL CORP0 citations61
US11527613B2Dec 13, 2022

Removal of a bottom-most nanowire from a nanowire device stack

INTEL CORP0 citations61
US10892326B2Jan 12, 2021

Removal of a bottom-most nanowire from a nanowire device stack

INTEL CORP0 citations61
US11923412B2Mar 5, 2024

Sub-fin leakage reduction for template strained materials

INTEL CORP0 citations59
US11600696B2Mar 7, 2023

Sub-fin leakage reduction for template strained materials

INTEL CORP0 citations59
US11495683B2Nov 8, 2022

Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

INTEL CORP0 citations59
US12294006B2May 6, 2025

Gate-all-around integrated circuit structures having insulator substrate

INTEL CORP0 citations52
US11688780B2Jun 27, 2023

Deep source and drain for transistor structures with back-side contact metallization

INTEL CORP0 citations52