Inventor
ERICKSON CHARLES R
US44 patents
⚠️ This page may combine multiple inventors who share the name “ERICKSON CHARLES R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
38 patentsUS5430687AJul 4, 1995
Programmable logic device including a parallel input device for loading memory cells
XILINX INC300 citations99
US6212639B1Apr 3, 2001
Encryption of configuration stream
XILINX INC85 citations98
US5969543AOct 19, 1999
Input signal interface with independently controllable pull-up and pull-down circuitry
XILINX INC90 citations98
US5970142AOct 19, 1999
Configuration stream encryption
XILINX INC102 citations98
US5815016ASep 29, 1998
Phase-locked delay loop for clock correction
XILINX INC151 citations98
US5801546ASep 1, 1998
Interconnect architecture for field programmable gate array using variable length conductors
XILINX INC114 citations98
US5646564AJul 8, 1997
Phase-locked delay loop for clock correction
XILINX INC122 citations98
US5581199ADec 3, 1996
Interconnect architecture for field programmable gate array using variable length conductors
XILINX INC155 citations98
US5523963AJun 4, 1996
Logic structure and circuit for fast carry
XILINX INC106 citations97
US6057704AMay 2, 2000
Partially reconfigurable FPGA and method of operating same
XILINX INC58 citations96
US5760604AJun 2, 1998
Interconnect architecture for field programmable gate array
XILINX INC38 citations96
US5640106AJun 17, 1997
Method and structure for loading data into several IC devices
XILINX INC142 citations96
US5600271AFeb 4, 1997
Input signal interface with independently controllable pull-up and pull-down circuitry
XILINX INC75 citations96
US5321704AJun 14, 1994
Error detection structure and method using partial polynomial check
XILINX INC56 citations96
US5631577AMay 20, 1997
Synchronous dual port RAM
XILINX INC88 citations95
US5598424AJan 28, 1997
Error detection structure and method for serial or parallel data stream using partial polynomial check
XILINX INC54 citations95
US5566123AOct 15, 1996
Synchronous dual port ram
XILINX INC90 citations95
US5838167ANov 17, 1998
Method and structure for loading data into several IC devices
XILINX INC89 citations94
US5760607AJun 2, 1998
System comprising field programmable gate array and intelligent memory
XILINX INC110 citations93
US5995988ANov 30, 1999
Configurable parallel and bit serial load apparatus
XILINX INC43 citations92
US5909453AJun 1, 1999
Lookahead structure for fast scan testing
XILINX INC30 citations92
US5844829ADec 1, 1998
Configurable parallel and bit serial load apparatus
XILINX INC23 citations92
US5742531AApr 21, 1998
Configurable parallel and bit serial load apparatus
XILINX INC18 citations92
US5694056ADec 2, 1997
Fast pipeline frame full detector
XILINX INC42 citations92
US5489858AFeb 6, 1996
Soft wakeup output buffer
XILINX INC36 citations92
US5331220AJul 19, 1994
Soft wakeup output buffer
XILINX INC27 citations92
US5140193AAug 18, 1992
Programmable connector for programmable logic device
XILINX INC53 citations92
US5923614AJul 13, 1999
Structure and method for reading blocks of data from selectable points in a memory device
XILINX INC24 citations91
US5920201AJul 6, 1999
Circuit for testing pumped voltage gates in a programmable gate array
XILINX INC30 citations91
US5789938AAug 4, 1998
Structure and method for reading blocks of data from selectable points in a memory device
XILINX INC15 citations81
US5961576AOct 5, 1999
Configurable parallel and bit serial load apparatus
XILINX INC13 citations74
US5410194AApr 25, 1995
Asynchronous or synchronous load multifunction flip-flop
XILINX INC13 citations74
US6181158B1Jan 30, 2001
Configuration logic to eliminate signal contention during reconfiguration
XILINX INC11 citations73
US5770951AJun 23, 1998
Configuration logic to eliminate signal contention during reconfiguration
XILINX INC6 citations73
US5592105AJan 7, 1997
Configuration logic to eliminate signal contention during reconfiguration
XILINX INC9 citations73
US5717340AFeb 10, 1998
Circuit for testing pumped voltage gates in a programmable gate array
XILINX INC12 citations72
US5990704ANov 23, 1999
Internal drive circuit providing third input pin state
XILINX INC3 citations62
US6100705AAug 8, 2000
Method and structure for viewing static signal levels on integrated circuits using electron beam deflection device
XILINX INC0 citations51