Inventor

LIN CHIN-SHEN

TW52 patents

⚠️ This page may combine multiple inventors who share the name “LIN CHIN-SHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN CHIN-SHEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Power grid structures and method of forming the same

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Integrated circuit design method, system and computer program product

Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same

Method for evaluating failure-in-time

Power grid of integrated circuit

Power rail for preventing DC electromigration

Method for analyzing electromigration (EM) in integrated circuit

Semiconductor arrangement and method of making

System and computer program product for integrated circuit design

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Circuit layouts and related methods

Power rail for preventing DC electromigration

Routing structure and method of forming the same

Method for analyzing electromigration (EM) in integrated circuit

Optimized electromigration analysis

Metal lines for preventing AC electromigration

Integrated circuit and method of forming the same

Method for evaluating failure-in-time

Integrated circuit and method of forming the same

Method for evaluating failure-in-time

Integrated circuit and method of forming the same

Method for evaluating failure-in-time

Conductive line structures and method of forming same

Semiconductor device including standard-cell-adapted power grid arrangement

Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof

Integrated circuit design method, system and computer program product

Integrated circuit device and method

Method of forming power grid structures

Method for analyzing electromigration (EM) in integrated circuit

Via sizing for IR drop reduction

Optimized electromigration analysis

Integrated circuit design method, system and computer program product

Via sizing for IR drop reduction

System and method for simulating reliability of circuit design

Method, system, and storage medium for RC extraction using hierarchical modeling architecture

Method, system and computer readable medium using stitching for mask assignment of patterns

Routing structure

Electromigration sign-off tool

Layouts for conductive layers in integrated circuits

Layouts for conductive layers in integrated circuits

Post-silicon tuning in voltage control of semiconductor integrated circuits

Voltage control of semiconductor integrated circuits

Electromigration sign-off tool

Electromigration sign-off methodology

Electromigration sign-off methodology

Method, system and computer readable medium using stitching for mask assignment of patterns

Semiconductor structure including boundary header cell and method for manufacturing the same

Method for analyzing an electromigration (EM) rule violation in an integrated circuit

TSENG HSIEN-YU

EDA tool and method, and integrated circuit formed by the method