Inventor

GURUMURTHI SUDHANVA

US30 patents

⚠️ This page may combine multiple inventors who share the name “GURUMURTHI SUDHANVA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GURUMURTHI SUDHANVA

ADVANCED MICRO DEVICES INC

System and method for protecting GPU memory instructions against faults

Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies

System and method for protecting GPU memory instructions against faults

Host-level error detection and fault correction

Selecting an error correction code type for a memory device

Software only inter-compute unit redundant multithreading for GPUs

Signature-based store checking buffer

Using sub-networks created from neural networks for processing color images

Error detection and correction in memory modules using programmable ECC engines

Error handling for resilient software

System and method for protecting GPU memory instructions against faults

Method and apparatus to support instruction replay for executing idempotent code in dependent processing in memory devices

Error checking data used in offloaded operations

Providing host-based error detection capabilities in a remote execution device

Error handling for resilient software

Hardware based redundant multi-threading inside a GPU for improved reliability

Method and apparatus for fault prediction and management

Error-tolerant memory system for machine learning systems

Method and system for memory attack mitigation

Software only intra-compute unit redundant multithreading for GPUs

Method and apparatus for generating artificial intelligence resistant verification images

Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scaling

Page retirement techniques for multi-page DRAM faults

Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scaling

Temperature-based adjustments for in-memory matrix multiplication

Determining the vulnerability of multi-threaded program code to soft errors

Using multiple functional blocks for training neural networks

Using redundant transactions to verify the correctness of program code execution

Runtime extension for neural network training with heterogeneous memory

INTEL CORP

Detecting errors in directory entries