Inventor

HWANG WEI

US88 patents

⚠️ This page may combine multiple inventors who share the name “HWANG WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HWANG WEI

IBM

Merged logic and memory combining thin film and bulk Si transistors

System-on-chip layout compilation

Method of fabricating cross-point lightly-doped drain-source trench transistor

System integration of DRAM macros and logic cores in a single chip architecture

Merged logic and memory combining thin film and bulk Si transistors

Data retention registers

Decoupling capacitor structure distributed above an integrated circuit and method for making same

Emulating quasi-synchronous DRAM with asynchronous DRAM

Method of forming double well substrate plate trench DRAM cell array

Power supply tracking regulator for a memory array

Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors

Forming a bit line configuration for semiconductor memory

Double well substrate plate trench DRAM cell array

Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors

Bit line configuration for semiconductor memory

CMOS off-chip driver circuits

Boost clock circuit for driving redundant wordlines and sample wordlines

Integrated trench-transistor structure and fabrication process

High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor

High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor

Method of self programmed built in self test

Method of making buried-sidewall-strap two transistor one capacitor trench cell

Stacked bit-line architecture for high density cross-point memory cell array

Cross-point lightly-doped drain-source trench transistor and fabrication process therefor

Method and system for selecting sizes of components for integrated circuits

Method for fabricating flash memory device using dual damascene process

Word line driver circuit for dynamic random access memories

High speed dynamic, random access memory with extended reset/precharge time

PMOS wordline boost cricuit for DRAM

Method for fabricating a mesa transistor-trench capacitor memory cell structure

High performance semiconductor memory device with low power consumption

Asynchronous multiport register file with self resetting write operation

Self programmed built in self test

Pulse-to-static conversion latch with a self-timed control circuit

Method of forming a buried-sidewall-strap two transistor one capacitor trench cell

High-performance differential cascode voltage switch with pass gate logic elements

Cells and read-circuits for high-performance register files

Bandgap voltage reference generator

Power supply tracking regulator for a memory array

Dram having extended refresh time

Wordline voltage boosting circuits for complementary MOSFET dynamic memories

Method and structure for a high density VMOS dynamic ram array

Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits

Dynamic ram having multiplexed twin I/O line pairs

Method and system for tuning of components for integrated circuits

Buried-sidewall-strap two transistor one capacitor trench cell

Fabrication method for a double trench memory cell device

UNIV NAT CHIAO TUNG

Multi-port SRAM with shared write bit-line architecture and selective read path for low power operation

Power gating structure having data retention and intermediate modes

CHUANG CHING-TE

Static random access memory with data controlled power supply