Inventor

ZBICIAK JOSEPH

US115 patents

Patents

50 patents

US9606803B2Mar 28, 2017

Highly integrated scalable, flexible DSP megamodule architecture

TEXAS INSTRUMENTS INC101 citations99

US10162641B2Dec 25, 2018

Highly integrated scalable, flexible DSP megamodule architecture

TEXAS INSTRUMENTS INC17 citations98

US9904645B2Feb 27, 2018

Multicore bus architecture with non-blocking high performance transaction credit system

TEXAS INSTRUMENTS INC65 citations98

US10203958B2Feb 12, 2019

Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets

TEXAS INSTRUMENTS INC4 citations84

US10318433B2Jun 11, 2019

Streaming engine with multi dimensional circular addressing selectable at each dimension

TEXAS INSTRUMENTS INC9 citations84

US10318293B2Jun 11, 2019

Predication methods for vector processors

TEXAS INSTRUMENTS INC7 citations84

US10078551B2Sep 18, 2018

Streaming engine with error detection, correction and restart

TEXAS INSTRUMENTS INC9 citations84

US10073696B2Sep 11, 2018

Streaming engine with cache-like stream data storage and lifetime tracking

TEXAS INSTRUMENTS INC9 citations84

US10061675B2Aug 28, 2018

Streaming engine with deferred exception reporting

TEXAS INSTRUMENTS INC10 citations84

US9965278B1May 8, 2018

Streaming engine with compressed encoding for loop circular buffer sizes

TEXAS INSTRUMENTS INC7 citations84

US6801985B1Oct 5, 2004

Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses

TEXAS INSTRUMENTS INC16 citations84

US6691240B1Feb 10, 2004

System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way

TEXAS INSTRUMENTS INC14 citations84

US10936317B2Mar 2, 2021

Streaming address generation

TEXAS INSTRUMENTS INC4 citations83

US6892380B2May 10, 2005

Method for software pipelining of irregular conditional control loops

TEXAS INSTRUMENTS INC14 citations83

US10901913B2Jan 26, 2021

Two address translations from a single table look-aside buffer read

TEXAS INSTRUMENTS INC1 citations82

US10140239B1Nov 27, 2018

Superimposing butterfly network controls for pattern combinations

TEXAS INSTRUMENTS INC11 citations82

US6754893B2Jun 22, 2004

Method for collapsing the prolog and epilog of software pipelined loops

TEXAS INSTRUMENTS INC14 citations82

US12360843B2Jul 15, 2025

Multicore shared cache operation engine

TEXAS INSTRUMENTS INC0 citations73

US12182573B2Dec 31, 2024

Processing device with vector transformation execution

TEXAS INSTRUMENTS INC1 citations73

US12072812B2Aug 27, 2024

Highly integrated scalable, flexible DSP megamodule architecture

TEXAS INSTRUMENTS INC0 citations73

US11847453B2Dec 19, 2023

Stream engine with element promotion and decimation modes

TEXAS INSTRUMENTS INC2 citations73

US11789742B2Oct 17, 2023

Pipeline protection for CPUs with save and restore of intermediate results

TEXAS INSTRUMENTS INC2 citations73

US11768685B2Sep 26, 2023

Processing device with vector transformation execution

TEXAS INSTRUMENTS INC2 citations73

US11709779B2Jul 25, 2023

Streaming engine with multi dimensional circular addressing selectable at each dimension

TEXAS INSTRUMENTS INC2 citations73

US11693661B2Jul 4, 2023

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

TEXAS INSTRUMENTS INC2 citations73

US11573847B2Feb 7, 2023

Streaming engine with deferred exception reporting

TEXAS INSTRUMENTS INC2 citations73

US11341052B2May 24, 2022

Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect

TEXAS INSTRUMENTS INC0 citations73

US11327761B2May 10, 2022

Processing device with vector transformation execution

TEXAS INSTRUMENTS INC3 citations73

US11226818B2Jan 18, 2022

Stream engine with element promotion and decimation modes

TEXAS INSTRUMENTS INC3 citations73

US11210097B2Dec 28, 2021

Stream reference register with double vector and dual single vector operating modes

TEXAS INSTRUMENTS INC3 citations73

US11182200B2Nov 23, 2021

Streaming engine with short cut start instructions

TEXAS INSTRUMENTS INC4 citations73

US11119779B2Sep 14, 2021

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

TEXAS INSTRUMENTS INC1 citations73

US11106463B2Aug 31, 2021

System and method for addressing data in memory

TEXAS INSTRUMENTS INC5 citations73

US11099933B2Aug 24, 2021

Streaming engine with error detection, correction and restart

TEXAS INSTRUMENTS INC3 citations73

US10990398B2Apr 27, 2021

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

TEXAS INSTRUMENTS INC4 citations73

US10908901B2Feb 2, 2021

Streaming engine with early exit from loop levels supporting early exit loops and irregular loops

TEXAS INSTRUMENTS INC2 citations73

US10810131B2Oct 20, 2020

Streaming engine with multi dimensional circular addressing selectable at each dimension

TEXAS INSTRUMENTS INC3 citations73

US10747636B2Aug 18, 2020

Streaming engine with deferred exception reporting

TEXAS INSTRUMENTS INC2 citations73

US10713174B2Jul 14, 2020

Streaming engine with early and late address and loop count registers to track architectural state

TEXAS INSTRUMENTS INC3 citations73

US10678545B2Jun 9, 2020

Data processing apparatus having streaming engine with read and read/advance operand coding

TEXAS INSTRUMENTS INC2 citations73

US10606598B2Mar 31, 2020

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

TEXAS INSTRUMENTS INC2 citations73

US10459843B2Oct 29, 2019

Streaming engine with separately selectable element and group duplication

TEXAS INSTRUMENTS INC2 citations73

Showing the top 50 of 115 patents by PatentIndex Score.

ZBICIAK JOSEPH

Patents

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Multicore bus architecture with non-blocking high performance transaction credit system

Streaming engine with stream metadata saving for context switching

Exposing valid byte lanes as vector predicates to CPU

Highly integrated scalable, flexible DSP megamodule architecture

Pipeline protection for CPUs with save and restore of intermediate results

Multicore shared cache operation engine

Streaming engine with error detection, correction and restart

Stream engine with element promotion and decimation modes

Butterfly network on load data return

Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets

Streaming engine with multi dimensional circular addressing selectable at each dimension

Predication methods for vector processors

Streaming engine with error detection, correction and restart

Streaming engine with cache-like stream data storage and lifetime tracking

Streaming engine with deferred exception reporting

Streaming engine with compressed encoding for loop circular buffer sizes

Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses

System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way

Streaming address generation

Method for software pipelining of irregular conditional control loops

Two address translations from a single table look-aside buffer read

Superimposing butterfly network controls for pattern combinations

Method for collapsing the prolog and epilog of software pipelined loops

Multicore shared cache operation engine

Processing device with vector transformation execution

Highly integrated scalable, flexible DSP megamodule architecture

Stream engine with element promotion and decimation modes

Pipeline protection for CPUs with save and restore of intermediate results

Processing device with vector transformation execution

Streaming engine with multi dimensional circular addressing selectable at each dimension

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Streaming engine with deferred exception reporting

Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect

Processing device with vector transformation execution

Stream engine with element promotion and decimation modes

Stream reference register with double vector and dual single vector operating modes

Streaming engine with short cut start instructions

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

System and method for addressing data in memory

Streaming engine with error detection, correction and restart

Mechanism for interrupting and resuming execution on an unprotected pipeline processor

Streaming engine with early exit from loop levels supporting early exit loops and irregular loops

Streaming engine with multi dimensional circular addressing selectable at each dimension

Streaming engine with deferred exception reporting

Streaming engine with early and late address and loop count registers to track architectural state

Data processing apparatus having streaming engine with read and read/advance operand coding

Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

Streaming engine with separately selectable element and group duplication