Inventor

JAYASENA NUWAN S

US51 patents

⚠️ This page may combine multiple inventors who share the name “JAYASENA NUWAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAYASENA NUWAN S

ADVANCED MICRO DEVICES INC

Die-stacked memory device with reconfigurable logic

Page migration in a 3D stacked hybrid memory

Die-stacked memory device with reconfigurable logic

Page migration in a hybrid memory device

Using processor types for processing interrupts in a computing device

Processor with host and slave operating modes stacked with memory

Query operations for stacked-die memory device

Per-page control of physical address space distribution among memory modules

Memory system with region-specific memory access scheduling

Prefetch kernels on a graphics processing unit

Interposer having a pattern of sites for mounting chiplets

Computation memory operations in a logic layer of a stacked memory

Scheduling memory accesses using an efficient row burst value

Mechanisms to bound the presence of cache blocks with specific properties in caches

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

Bucketized hash tables with remap entries

Cluster-based migration in a multi-level memory hierarchy

Efficient accesses of data structures using processing near memory

Interconnect architecture for three-dimensional processing systems

Prefetch kernels on data-parallel processors

Prefetch kernels on data-parallel processors

Interconnect architecture for three-dimensional processing systems

Processing engine for complex atomic operations

Media content modification using user profiles

Memory page attribute modification

Resource access control

Memory system with region-specific memory access scheduling

Predicates for processing-in-memory

Cuckoo filters and cuckoo hash tables with biasing, compression, and decoupled logical sparsity

Memory system with region-specific memory access scheduling

Method and system for asymmetrical processing with managed data affinity

Adaptive scheduling of memory and processing-in-memory requests

Scheduling processing-in-memory requests and memory requests

Programmable data storage memory hierarchy

Bank-level parallelism for processing in memory

Data-driven precision for memory access

Fused data generation and associated communication

Compiler-assisted inter-SIMD-group register sharing

Processor with host and slave operating modes stacked with memory

Query operations for stacked-die memory device

Write endurance management techniques in the logic layer of a stacked memory

Dynamic adaptation of memory page management policy

Instruction set architecture and software support for register state migration

Power gating based on cache dirtiness

Configuring idle states for entities in a computing device based on predictions of durations of idle periods

Data distribution among multiple managed memories

HARTOG ROBERT SCOTT

Method for urgency-based preemption of a process

Software mechanisms for managing task scheduling on an accelerated processing device (APD)

LOH GABRIEL H

Die-stacked memory device providing data translation

GUMMARAJU JAYANTH

Scheduling compute kernel workgroups to heterogeneous processors based on historical processor execution times and utilizations