Inventor

TSENG HUAI-YUAN

US106 patents

⚠️ This page may combine multiple inventors who share the name “TSENG HUAI-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSENG HUAI-YUAN

SANDISK TECHNOLOGIES LLC

First read countermeasures in memory

Countermeasure for reducing peak current during program operation under first read condition

Countermeasures for first read issue

Negative voltage wordline methods and systems

Sub-block mode for non-volatile memory

Hole pre-charge scheme using gate induced drain leakage generation

Source side precharge and boosting improvement for reverse order program

Read operation for non-volatile memory with compensation for adjacent wordline

Row dependent sensing in nonvolatile memory

Power management for multi-plane read operations

Erase operation for memory device with staircase word line voltage during erase pulse

Programming process combining adaptive verify with normal and slow programming speeds in a memory device

Dynamic 1-tier scan for high performance 3D NAND

Interleaved program and verify in non-volatile memory

Peak current suppression

Asymmetric voltage ramp rate control

Bit line control that reduces select gate transistor disturb in erase operations

First read countermeasures in memory

State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device

Non-volatile memory with fast multi-level program verify

Memory apparatus and method of operation using negative kick clamp for fast read

Lockout mode for reverse order read operation

Dynamic staggering for programming in nonvolatile memory

Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations

Non-volatile memory with switchable erase methods

Look neighbor ahead for data recovery

Systems and methods for program verification on a memory system

Neighboring or logical minus word line dependent verify with sense time in programming of non-volatile memory

Programming process combining adaptive verify with normal and slow programming speeds in a memory device

Memory disturb detection

Programming selection devices in non-volatile memory strings

Memory device with connected word lines for fast programming

Adaptive programming voltage for non-volatile memory devices

Adaptive control of memory cell programming voltage

System and method for in-situ programming and read operation adjustments in a non-volatile memory

Erase tail comparator scheme

SANDISK TECHNOLOGIES INC

Smart skip verify mode for programming a memory device

Multi-die programming with die-jumping induced periodic delays

Double lockout in non-volatile memory

Non-volatile memory with prior state sensing

Dynamic threshold voltage compaction for non-volatile memory

Non-volatile memory with two phased programming

Error detection method

Compensating source side resistance versus word line

WESTERN DIGITAL TECH INC

Reducing post-read disturb in a nonvolatile memory device

Ramp rate control for peak and average current reduction of open blocks

Pre-charge timing control for peak current based on data latch count

Multi-stage voltage control for peak and average current reduction of open blocks

IND TECH RES INST

Image display with photo sensor

Pixel array with flexible circuit layout having respective scan and data line profiles with predetermined wave construction so as to evenly distribute any strain on the respective scan and data lines to withstand stress and be flexible