Inventor
DUH JIANN-JENG
US7 patents
Patents
7 patentsUS6778454B2Aug 17, 2004
FIFO memory devices that support all combinations of DDR and SDR read and write modes
INTEGRATED DEVICE TECH39 citations94
US7158440B2Jan 2, 2007
FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation
INTEGRATED DEVICE TECH16 citations90
US6795360B2Sep 21, 2004
Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes
INTEGRATED DEVICE TECH29 citations90
US7246300B1Jul 17, 2007
Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation
INTEGRATED DEVICE TECH10 citations82
US7093047B2Aug 15, 2006
Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration
INTEGRATED DEVICE TECH12 citations82
US7076610B2Jul 11, 2006
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same
INTEGRATED DEVICE TECH7 citations72
US7209983B2Apr 24, 2007
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation
INTEGRATED DEVICE TECH9 citations68